Tilera tile-gx events

This is a list of all tile-gx CPU's performance counter event types. Please see Tilera development doc: Multicore Development Environment Optimization Guide. Contact Tilera Corporation or visit http://www.tilera.com for more information.

Name	Description	Counters usable	Unit mask options
ZERO	Always zero - no event ever happens	all
ONE	Always one - an event occurs every cycle	all
PASS_WRITTEN	The event indicates that the PASS SPR was written	all
FAIL_WRITTEN	The event indicates that the FAIL SPR was written	all
DONE_WRITTEN	The event indicates that the DONE SPR was written	all
L1D_FILL_STALL	The event occurs when a memory operation stalls due to L1 DCache being busy doing a fill.	all
LOAD_HIT_STALL	The event occurs when an instruction 2 cycles after a load stalls due to a source operand being the destination. The L1 DCache hit latency is two cycles, so the instruction would stall on a miss but not on a hit.	all
LOAD_STALL	The event occurs when an instruction stalls due to a source operand being the destination of a load instruction. This event happens on all cycles that stall except for the one 2 cycles after the load, which is counted by LOAD_HIT_STALL event.	all
ALU_SRC_STALL	The event occurs when an instruction stalls due to a source operand being the destination of an ALU instruction.	all
IDN_SRC_STALL	The event occurs when an instruction stalls due to IDN source register not available.	all
UDN_SRC_STALL	The event occurs when an instruction stalls due to UDN source register not available.	all
MF_STALL	The event during stalls for Memory Fence instruction.	all
SLOW_SPR_STALL	The event occurs during stalls to slow SPR access.	all
NETWORK_DEST_STALL	The event occurs when a valid instruction in pipeline Decode stage stalls due to network destination full.	all
INSTRUCTION_STALL	The event occurs when a valid instruction in pipeline Decode stage stalls for any reason.	all
ITLB_MISS_INTERRUPT	The event occurs when an ITLB_MISS interrupt is taken.	all
INTERRUPT	The event occurs when any interrupt is taken.	all
INSTRUCTION_BUNDLE	The event occurs when there is a valid instruction in pipeline WB stage (e.g. when an instruction is commited).	all
TLB	The event occurs when a data memory operation is issued and the data translation lookaside buffer (DTLB) is used to translate the virtual address into the physical address.	all
READ	The event occurs when a load is issued.	all
WRITE	The event occurs when a store is issed.	all
TLB_EXCEPTION	The event occurs when the address of a data stream memory operation causes a Data TLB Exception including TLB Misses and protection violations.	all
READ_MISS	The event occurs when a load is issued and data is not returned from the level 1 data cache.	all
WRITE_MISS	The event occurs when a store is issued and the 16-byte aligned block (level 1 data cache line size) containing the address is not present at the level 1 data cache.	all
SNOOP_INCREMENT_READ	The event occurs when a read request is received from another Tile off the SDN and the Level 3 cache will track the share state.	all
SNOOP_NON_INCREMENT_READ	The event occurs when a read request is received from another Tile off the SDN and the Level 3 cache will not track the share state.	all
SNOOP_WRITE	The event occurs when a write request is received from another Tile off the SDN.	all
SNOOP_IO_READ	The event occurs when a read request is received from an IO device off the SDN.	all
SNOOP_IO_WRITE	The event occurs when a write request is received from an IO device off the SDN.	all
LOCAL_DATA_READ	The event occurs when a data read request is received from the main processor and the Level 3 cache resides in the Tile.	all
LOCAL_WRITE	The event occurs when a write request is received from the main processor and the Level 3 cache resides in the Tile.	all
LOCAL_INSTRUCTION_READ	The event occurs when an instruction read request is received from the main processor and the Level 3 cache resides in the Tile.	all
REMOTE_DATA_READ	The event occurs when a data read request is received from the main processor and the Level 3 cache resides in another Tile.	all
REMOTE_WRITE	The event occurs when a write request is received from the main processor and the Level 3 cache resides in another Tile.	all
REMOTE_INSTRUCTION_READ	The event occurs when an instruction read request is received from the main processor and the Level 3 cache resides in another Tile.	all
COHERENCE_INVALIDATION	The event occurs when a coherence invalidation is received from another Tile off the QDN.	all
SNOOP_INCREMENT_READ_MISS	The event occurs when a read request is received from another Tile off the SDN and misses the Level 3 cache. The level 3 cache will track the share state.	all
SNOOP_NON_INCREMENT_READ_MISS	The event occurs when a read request is received from another Tile off the SDN and misses the Level 3 cache. The Level 3 cache will not track the share state.	all
SNOOP_WRITE_MISS	The event occurs when a write request is received from another Tile off the SDN and misses the Level 3 cache.	all
SNOOP_IO_READ_MISS	The event occurs when a read request is received from an IO device off the SDN and misses the Level 3 cache.	all
SNOOP_IO_WRITE_MISS	The event occurs when a write request is received from an IO device off the SDN and misses the Level 3 cache.	all
LOCAL_DATA_READ_MISS	The event occurs when a data read request is received from the main processor and misses the Level 3 cache resided in the Tile.	all
LOCAL_WRITE_MISS	The event occurs when a write request is received from the main processor and misses the Level 3 cache resided in the Tile.	all
LOCAL_INSTRUCTION_READ_MISS	The event occurs when an instruction read request is received from the main processor and misses the Level 3 cache resided in the Tile.	all
REMOTE_DATA_READ_MISS	The event occurs when a data read request is received from the main processor and misses the Level 2 cache. The Level 3 cache resides in another Tile.	all
REMOTE_WRITE_MISS	The event occurs when a write request is received from the main processor and misses the Level 2 cache. The Level 3 cache resides in another Tile.	all
REMOTE_INSTRUCTION_READ_MISS	The event occurs when an instruction read request is received from the main processor and misses the Level 2 cache. The Level 3 cache resides in another Tile.	all
COHERENCE_INVALIDATION_HIT	The event occurs when a coherence invalidation is received from another Tile off the QDN and hits the level 2 cache.	all
CACHE_WRITEBACK	The event occurs when a cache writeback to main memory, including victim writes or explicit flushes, leaves the Tile.	all
SDN_STARVED	The event occurs when a snoop is received and the controller enters the SDN starved condition.	all
RDN_STARVED	The event occurs when the controller enters the RDN starved condition.	all
QDN_STARVED	The event occurs when the controller enters the QDN starved condition.	all
SKF_STARVED	The event occurs when the controller enters the skid FIFO starved condition.	all
RTF_STARVED	The event occurs when the controller enters the re-try FIFO starved condition.	all
IREQ_STARVED	The event occurs when the controller enters the instruction stream starved condition.	all
LOCAL_WRITE_BUFFER_ALLOC	The event occurs when a write request is received from the main processor and allocates a write buffer in the Level 3 cache resided in the Tile.	all
REMOTE_WRITE_BUFFER_ALLOC	The event occurs when a write request is received from the main processor and allocates a write buffer in the Level 2 cache resided in the Tile. The Level 3 cache resides in another Tile	all
UDN_PACKET_SENT	Main processor finished sending a packet to the UDN.	all
UDN_WORD_SENT	UDN word sent to an output port. Participating ports are selected with the UDN_EVT_PORT_SEL field.	all
UDN_BUBBLE	Bubble detected on an output port. A bubble is defined as a cycle in which no data is being sent, but the first word of a packet has already traversed the switch. Participating ports are selected with the UDN_EVT_PORT_SEL field.	all
UDN_CONGESTION	Out of credit on an output port. Participating ports are selected with the UDN_EVT_PORT_SEL field.	all
IDN_PACKET_SENT	Main processor finished sending a packet to the IDN.	all
IDN_WORD_SENT	IDN word sent to an output port. Participating ports are selected with the IDN_EVT_PORT_SEL field.	all
IDN_BUBBLE	Bubble detected on an output port. A bubble is defined as a cycle in which no data is being sent, but the first word of a packet has already traversed the switch. Participating ports are selected with the IDN_EVT_PORT_SEL field.	all
IDN_CONGESTION	Out of credit on an output port. Participating ports are selected with the IDN_EVT_PORT_SEL field.	all
RDN_PACKET_SENT	Main processor finished sending a packet to the RDN.	all
RDN_WORD_SENT	RDN word sent to an output port. Participating ports are selected with the RDN_EVT_PORT_SEL field.	all
RDN_BUBBLE	Bubble detected on an output port. A bubble is defined as a cycle in which no data is being sent, but the first word of a packet has already traversed the switch. Participating ports are selected with the RDN_EVT_PORT_SEL field.	all
RDN_CONGESTION	Out of credit on an output port. Participating ports are selected with the RDN_EVT_PORT_SEL field.	all
SDN_PACKET_SENT	Main processor finished sending a packet to the SDN.	all
SDN_WORD_SENT	SDN word sent to an output port. Participating ports are selected with the SDN_EVT_PORT_SEL field.	all
SDN_BUBBLE	Bubble detected on an output port. A bubble is defined as a cycle in which no data is being sent, but the first word of a packet has already traversed the switch. Participating ports are selected with the SDN_EVT_PORT_SEL field.	all
SDN_CONGESTION	Out of credit on an output port. Participating ports are selected with the SDN_EVT_PORT_SEL field.	all
QDN_PACKET_SENT	Main processor finished sending a packet to the QDN.	all
QDN_WORD_SENT	QDN word sent to an output port. Participating ports are selected with the QDN_EVT_PORT_SEL field.	all
QDN_BUBBLE	Bubble detected on an output port. A bubble is defined as a cycle in which no data is being sent, but the first word of a packet has already traversed the switch. Participating ports are selected with the QDN_EVT_PORT_SEL field.	all
QDN_CONGESTION	Out of credit on an output port. Participating ports are selected with the QDN_EVT_PORT_SEL field.	all
UDN_DEMUX_STALL	UDN Demux stalled due to buffer full	all
IDN_DEMUX_STALL	IDN Demux stalled due to buffer full	all