ppc64 POWER9 events

This is a list of all ppc64 POWER9's performance counter event types.

Name	Description	Counters usable
SW_INCR	Software increment of PMNC registers	1, 2, 3, 4, 5, 6
L1I_CACHE_REFILL	Level 1 instruction cache refill	1, 2, 3, 4, 5, 6
L1I_TLB_REFILL	Level 1 instruction TLB refill	1, 2, 3, 4, 5, 6
L1D_CACHE_REFILL	Level 1 data cache refill	1, 2, 3, 4, 5, 6
L1D_CACHE	Level 1 data cache access	1, 2, 3, 4, 5, 6
L1D_TLB_REFILL	Level 1 data TLB refill	1, 2, 3, 4, 5, 6
LD_RETIRED	Load instruction architecturally executed, condition code pass	1, 2, 3, 4, 5, 6
ST_RETIRED	Store instruction architecturally executed, condition code pass	1, 2, 3, 4, 5, 6
INST_RETIRED	Instruction architecturally executed	1, 2, 3, 4, 5, 6
EXC_TAKEN	Exception taken	1, 2, 3, 4, 5, 6
EXC_RETURN	Exception return instruction architecturally executed	1, 2, 3, 4, 5, 6
CID_WRITE_RETIRED	Write to CONTEXTIDR register architecturally executed	1, 2, 3, 4, 5, 6
PC_WRITE_RETIRED	Software change of the PC architecturally executed, condition code pass	1, 2, 3, 4, 5, 6
BR_IMMED_RETIRED	Immediate branch instruction architecturally executed	1, 2, 3, 4, 5, 6
BR_RETURN_RETIRED	Procedure return instruction architecturally executed, condition code pass	1, 2, 3, 4, 5, 6
UNALIGNED_LDST_RETIRED	Unaligned load or store instruction architecturally executed, condition code pass	1, 2, 3, 4, 5, 6
BR_MIS_PRED	Mispredicted or not predicted branch speculatively executed	1, 2, 3, 4, 5, 6
BR_PRED	Predictable branch speculatively executed	1, 2, 3, 4, 5, 6
MEM_ACCESS	Data memory access	1, 2, 3, 4, 5, 6
L1I_CACHE	Level 1 instruction cache access	1, 2, 3, 4, 5, 6
L1D_CACHE_WB	Level 1 data cache write-back	1, 2, 3, 4, 5, 6
L2D_CACHE	Level 2 data cache access	1, 2, 3, 4, 5, 6
L2D_CACHE_REFILL	Level 2 data cache refill	1, 2, 3, 4, 5, 6
L2D_CACHE_WB	Level 2 data cache write-back	1, 2, 3, 4, 5, 6
BUS_ACCESS	Bus access	1, 2, 3, 4, 5, 6
MEMORY_ERROR	Local memory error	1, 2, 3, 4, 5, 6
INST_SPEC	Instruction speculatively executed	1, 2, 3, 4, 5, 6
TTBR_WRITE_RETIRED	Write to TTBR architecturally executed, condition code pass	1, 2, 3, 4, 5, 6
BUS_CYCLES	Bus cycle	1, 2, 3, 4, 5, 6
CPU_CYCLES	CPU cycle	0
L1D_CACHE_LD	Level 1 data cache access, read	1, 2, 3, 4, 5, 6
L1D_CACHE_ST	Level 1 data cache access, write	1, 2, 3, 4, 5, 6
L2D_CACHE_LD	Level 2 data cache access, read	1, 2, 3, 4, 5, 6
L2D_CACHE_ST	Level 2 data cache access, write	1, 2, 3, 4, 5, 6
L2D_CACHE_WB_VICTIM	Level 2 data cache write-back, victim	1, 2, 3, 4, 5, 6
L2D_CACHE_WB_CLEAN	Level 2 data cache write-back, cleaning and coherency	1, 2, 3, 4, 5, 6
L2D_CACHE_INVAL	Level 2 data cache invalidate	1, 2, 3, 4, 5, 6
BUS_ACCESS_SHARED	Bus access, normal, cacheable, shareable	1, 2, 3, 4, 5, 6
BUS_ACCESS_NOT_SHARED	Bus access, not normal, cacheable, shareable	1, 2, 3, 4, 5, 6
BUS_ACCESS_NORMAL	Bus access, normal	1, 2, 3, 4, 5, 6
BUS_ACCESS_PERIPH	Bus access, peripheral	1, 2, 3, 4, 5, 6
MEM_ACCESS_LD	Data memory access, read	1, 2, 3, 4, 5, 6
MEM_ACCESS_ST	Data memory access, write	1, 2, 3, 4, 5, 6
UNALIGNED_LD_SPEC	Unaligned access, read	1, 2, 3, 4, 5, 6
UNALIGNED_ST_SPEC	Unaligned access, write	1, 2, 3, 4, 5, 6
UNALIGNED_LDST_SPEC	Unaligned access	1, 2, 3, 4, 5, 6
LDREX_SPEC	ldrex instruction speculatively executed	1, 2, 3, 4, 5, 6
STREX_FAIL_SPEC	strex instruction speculatively executed, fail	1, 2, 3, 4, 5, 6
STREX_SPEC	strex instruction speculatively executed	1, 2, 3, 4, 5, 6
LD_SPEC	Load instruction speculatively executed	1, 2, 3, 4, 5, 6
ST_SPEC	Store instruction speculatively executed	1, 2, 3, 4, 5, 6
LDST_SPEC	Load or store instruction speculatively executed	1, 2, 3, 4, 5, 6
DP_SPEC	Data processing instruction speculatively executed	1, 2, 3, 4, 5, 6
ASE_SPEC	Advanced SIMD extension instruction speculatively executed	1, 2, 3, 4, 5, 6
VFP_SPEC	Floating-point extension instruction speculatively executed	1, 2, 3, 4, 5, 6
PC_WRITE_SPEC	Software change of the PC instruction speculatively executed	1, 2, 3, 4, 5, 6
BR_IMMED_SPEC	Immediate branch instruction speculatively executed	1, 2, 3, 4, 5, 6
BR_RETURN_SPEC	Procedure return instruction speculatively executed	1, 2, 3, 4, 5, 6
BR_INDIRECT_SPEC	Indirect branch instruction speculatively executed	1, 2, 3, 4, 5, 6
ISB_SPEC	ISB barrier instruction speculatively executed	1, 2, 3, 4, 5, 6
DSB_SPEC	DSB barrier instruction speculatively executed	1, 2, 3, 4, 5, 6
DMB_SPEC	DMB barrier instruction speculatively executed	1, 2, 3, 4, 5, 6
EXC_UNDEF	Exception taken, Undefined Instruction	1, 2, 3, 4, 5, 6
EXC_HVC	Exception taken, Hypervisor Call	1, 2, 3, 4, 5, 6
LF_STALL	Linefill caused an instruction side stall	1, 2, 3, 4, 5, 6
PTW_STALL	Translation table walk caused an instruction side stall	1, 2, 3, 4, 5, 6
I_TAG_RAM_RD	Number of set of 4 ways read in the instruction cache - Tag RAM	1, 2, 3, 4, 5, 6
I_DATA_RAM_RD	Number of ways read in the instruction cache - Data RAM	1, 2, 3, 4, 5, 6
I_BTAC_RAM_RD	Number of ways read in the instruction BTAC RAM	1, 2, 3, 4, 5, 6
DATA_SNOOP	Data snooped from other processor	1, 2, 3, 4, 5, 6
D_LSU_SLOT_FULL	Duration during which all slots in the Load-Store Unit are busy	1, 2, 3, 4, 5, 6
LS_IQ_FULL	Duration during which all slots in the Load-Store Issue queue are busy	1, 2, 3, 4, 5, 6
DP_IQ_FULL	Duration during which all slots in the Data Processing issue queue are busy.	1, 2, 3, 4, 5, 6
DE_IQ_FULL	Duration during which all slots in the Data Engine issue queue are busy	1, 2, 3, 4, 5, 6
FLUSH_DE_NEON	Number of NEON instruction which fail their condition code and lead to a flush of the DE pipe	1, 2, 3, 4, 5, 6
EXC_TRAP_HYP	Number of Trap to hypervisor	1, 2, 3, 4, 5, 6
ETM_EXT_OUT0	PTM EXTOUT 0	1, 2, 3, 4, 5, 6
ETM_EXT_OUT1	PTM EXTOUT 1	1, 2, 3, 4, 5, 6
MMU_PTW	Duration during which the MMU handle a translation table walk.	1, 2, 3, 4, 5, 6
MMU_PTW_ST1	Duration during which the MMU handle a Stage1 translation table walk	1, 2, 3, 4, 5, 6
MMU_PTW_ST2	Duration during which the MMU handle a Stage2 translation table walk	1, 2, 3, 4, 5, 6
MMU_PTW_LSU	Duration during which the MMU handle a translation table walk requested by the Load Store Unit	1, 2, 3, 4, 5, 6
MMU_PTW_ISIDE	Duration during which the MMU handle a translation table walk requested by the Instruction side	1, 2, 3, 4, 5, 6
MMU_PTW_PLD	Duration during which the MMU handle a translation table walk requested by a Preload instruction or Prefetch request	1, 2, 3, 4, 5, 6
MMU_PTW_CP15	Duration during which the MMU handle a translation table walk requested by a CP15 operation	1, 2, 3, 4, 5, 6
PLD_UTLB_REFILL	Level 1 PLD TLB refill	1, 2, 3, 4, 5, 6
CP15_UTLB_REFILL	Level 1 CP15 TLB refil	1, 2, 3, 4, 5, 6
UTLB_FLUSH	Level 1 TLB flus	1, 2, 3, 4, 5, 6
TLB_ACCESS	Level 2 TLB access	1, 2, 3, 4, 5, 6
TLB_MISS	Level 2 TLB miss	1, 2, 3, 4, 5, 6