This is a list of all ppc64 POWER8's performance counter event types.
| Name | Description | Counters usable | |
| CYCLES | Cycles | 0 | |
| PM_1PLUS_PPC_CMPL | 1 or more ppc insts finished (completed). | 0 | |
| PM_1PLUS_PPC_DISP | Cycles at least one Instr Dispatched. Could be a group with only microcode. Issue HW016521 | 3 | |
| PM_ANY_THRD_RUN_CYC | Any thread in run_cycles (was one thread in run_cycles). | 0 | |
| PM_BR_MPRED_CMPL | Number of Branch Mispredicts. | 3 | |
| PM_BR_TAKEN_CMPL | Branch Taken. | 1 | |
| PM_CYC | Cycles . | 0, 1, 2, 3 | |
| PM_DATA_FROM_L2MISS | Demand LD - L2 Miss (not L2 hit). | 1 | |
| PM_DATA_FROM_L3MISS | Demand LD - L3 Miss (not L2 hit and not L3 hit). | 2 | |
| PM_DATA_FROM_MEM | Data cache reload from memory (including L4). | 3 | |
| PM_DTLB_MISS | Data PTEG Reloaded (DTLB Miss). | 2 | |
| PM_EXT_INT | external interrupt. | 1 | |
| PM_FLOP | Floating Point Operations Finished. | 0 | |
| PM_FLUSH | Flush (any type). | 3 | |
| PM_GCT_NOSLOT_CYC | Pipeline empty (No itags assigned , no GCT slots used). | 0 | |
| PM_IERAT_RELOAD | IERAT Reloaded (Miss). | 0 | |
| PM_INST_DISP | PPC Dispatched. | 1 | |
| PM_INST_FROM_L3MISS | Inst from L3 miss. | 2 | |
| PM_ITLB_MISS | ITLB Reloaded. | 3 | |
| PM_L1_DCACHE_RELOAD_VALID | DL1 reloaded due to Demand Load . | 2 | |
| PM_L1_ICACHE_MISS | Demand iCache Miss. | 1 | |
| PM_LD_MISS_L1 | Load Missed L1. | 2 | |
| PM_LSU_DERAT_MISS | DERAT Reloaded (Miss). | 1 | |
| PM_MRK_BR_MPRED_CMPL | Marked Branch Mispredicted. | 2 | |
| PM_MRK_BR_TAKEN_CMPL | Marked Branch Taken. | 0 | |
| PM_MRK_DATA_FROM_L2MISS | Data cache reload L2 miss. | 3 | |
| PM_MRK_DATA_FROM_L3MISS | The processor's data cache was reloaded from a localtion other than the local core's L3 due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_MEM | The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load. | 1 | |
| PM_MRK_DERAT_MISS | Erat Miss (TLB Access) All page sizes. | 2 | |
| PM_MRK_DTLB_MISS | Marked dtlb miss. | 3 | |
| PM_MRK_INST_CMPL | marked instruction completed. | 3 | |
| PM_MRK_INST_DISP | Marked Instruction dispatched. | 0 | |
| PM_MRK_INST_FROM_L3MISS | n/a | 3 | |
| PM_MRK_L1_ICACHE_MISS | Marked L1 Icache Miss. | 0 | |
| PM_MRK_L1_RELOAD_VALID | Marked demand reload. | 0 | |
| PM_MRK_LD_MISS_L1 | Marked DL1 Demand Miss counted at exec time. | 1 | |
| PM_MRK_ST_CMPL | Marked store completed. | 0 | |
| PM_RUN_CYC | Run_cycles. | 5 | |
| PM_RUN_INST_CMPL | Run_Instructions. | 4 | |
| PM_RUN_PURR | Run_PURR. | 3 | |
| PM_ST_FIN | Store Instructions Finished (store sent to nest). | 1 | |
| PM_ST_MISS_L1 | Store Missed L1. | 2 | |
| PM_TB_BIT_TRANS | timebase event. | 2 | |
| PM_THRD_CONC_RUN_INST | Concurrent Run Instructions. | 2 | |
| PM_THRESH_EXC_1024 | Threshold counter exceeded a value of 1024. | 2 | |
| PM_THRESH_EXC_128 | Threshold counter exceeded a value of 128. | 3 | |
| PM_THRESH_EXC_2048 | Threshold counter exceeded a value of 2048. | 3 | |
| PM_THRESH_EXC_256 | Threshold counter exceed a count of 256. | 0 | |
| PM_THRESH_EXC_32 | Threshold counter exceeded a value of 32. | 1 | |
| PM_THRESH_EXC_4096 | Threshold counter exceed a count of 4096. | 0 | |
| PM_THRESH_EXC_512 | Threshold counter exceeded a value of 512. | 1 | |
| PM_THRESH_EXC_64 | Threshold counter exceeded a value of 64. | 2 | |
| PM_THRESH_MET | threshold exceeded. | 0 | |
| PM_1LPAR_CYC | Number of cycles in single lpar mode. | 0 | |
| PM_2LPAR_CYC | Number of cycles in 2 lpar mode. | 1 | |
| PM_4LPAR_CYC | Number of cycles in 4 LPAR mode. | 3 | |
| PM_ALL_CHIP_PUMP_CPRED | Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for all data types ( demand load,data,inst prefetch,inst fetch,xlate (I or d) | 0 | |
| PM_ALL_GRP_PUMP_CPRED | Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) | 1 | |
| PM_ALL_GRP_PUMP_MPRED | got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro | 1 | Final Pump ScopeGroup to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) |
| PM_ALL_GRP_PUMP_MPRED_RTY | to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) | 0 | Final Pump ScopeGroup |
| PM_ALL_PUMP_CPRED | Pump prediction correct. Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) | 0 | |
| PM_ALL_PUMP_MPRED | Pump Mis prediction Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) | 3 | |
| PM_ALL_SYS_PUMP_CPRED | Initial and Final Pump Scope and data sourced across this scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) | 2 | |
| PM_ALL_SYS_PUMP_MPRED | Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or | 2 | |
| PM_ALL_SYS_PUMP_MPRED_RTY | Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate) | 3 | |
| PM_BACK_BR_CMPL | Branch instruction completed with a target address less than current instruction address. | 1 | |
| PM_BANK_CONFLICT | Read blocked due to interleave conflict. The ifar logic will detect an interleave conflict and kill the data that was read that cycle. | 0, 1, 2, 3 | |
| PM_BRU_FIN | Branch Instruction Finished . | 0 | |
| PM_BR_2PATH | two path branch. | 1 | |
| PM_BR_BC_8 | Pairable BC+8 branch that has not been converted to a Resolve Finished in the BRU pipeline | 0, 1, 2, 3 | |
| PM_BR_BC_8_CONV | Pairable BC+8 branch that was converted to a Resolve Finished in the BRU pipeline. | 0, 1, 2, 3 | |
| PM_BR_CMPL | Branch Instruction completed. | 3 | |
| PM_BR_MPRED_CCACHE | Conditional Branch Completed that was Mispredicted due to the Count Cache Target Prediction | 0, 1, 2, 3 | |
| PM_BR_MPRED_CR | Conditional Branch Completed that was Mispredicted due to the BHT Direction Prediction (taken/not taken). | 0, 1, 2, 3 | |
| PM_BR_MPRED_LSTACK | Conditional Branch Completed that was Mispredicted due to the Link Stack Target Prediction | 0, 1, 2, 3 | |
| PM_BR_MPRED_TA | Conditional Branch Completed that was Mispredicted due to the Target Address Prediction from the Count Cache or Link Stack. Only XL-form branches that resolved Taken set this event. | 0, 1, 2, 3 | |
| PM_BR_MRK_2PATH | marked two path branch. | 0 | |
| PM_BR_PRED_BR0 | Conditional Branch Completed on BR0 (1st branch in group) in which the HW predicted the Direction or Target | 0, 1, 2, 3 | |
| PM_BR_PRED_BR1 | Conditional Branch Completed on BR1 (2nd branch in group) in which the HW predicted the Direction or Target. Note: BR1 can only be used in Single Thread Mode. In all of the SMT modes, only one branch can complete, thus BR1 is unused. | 0, 1, 2, 3 | |
| PM_BR_PRED_BR_CMPL | IFU | 0, 1, 2, 3 | |
| PM_BR_PRED_CCACHE_BR0 | Conditional Branch Completed on BR0 that used the Count Cache for Target Prediction | 0, 1, 2, 3 | |
| PM_BR_PRED_CCACHE_BR1 | Conditional Branch Completed on BR1 that used the Count Cache for Target Prediction | 0, 1, 2, 3 | |
| PM_BR_PRED_CCACHE_CMPL | IFU | 0, 1, 2, 3 | |
| PM_BR_PRED_CR_BR0 | Conditional Branch Completed on BR0 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and bra | 0, 1, 2, 3 | |
| PM_BR_PRED_CR_BR1 | Conditional Branch Completed on BR1 that had its direction predicted. I-form branches do not set this event. In addition, B-form branches which do not use the BHT do not set this event - these are branches with BO-field set to 'always taken' and bra | 0, 1, 2, 3 | |
| PM_BR_PRED_CR_CMPL | IFU | 0, 1, 2, 3 | |
| PM_BR_PRED_LSTACK_BR0 | Conditional Branch Completed on BR0 that used the Link Stack for Target Prediction | 0, 1, 2, 3 | |
| PM_BR_PRED_LSTACK_BR1 | Conditional Branch Completed on BR1 that used the Link Stack for Target Prediction | 0, 1, 2, 3 | |
| PM_BR_PRED_LSTACK_CMPL | IFU | 0, 1, 2, 3 | |
| PM_BR_PRED_TA_BR0 | Conditional Branch Completed on BR0 that had its target address predicted. Only XL-form branches set this event. | 0, 1, 2, 3 | |
| PM_BR_PRED_TA_BR1 | Conditional Branch Completed on BR1 that had its target address predicted. Only XL-form branches set this event. | 0, 1, 2, 3 | |
| PM_BR_PRED_TA_CMPL | IFU | 0, 1, 2, 3 | |
| PM_BR_UNCOND_BR0 | Unconditional Branch Completed on BR0. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve. | 0, 1, 2, 3 | |
| PM_BR_UNCOND_BR1 | Unconditional Branch Completed on BR1. HW branch prediction was not used for this branch. This can be an I-form branch, a B-form branch with BO-field set to branch always, or a B-form branch which was coverted to a Resolve. | 0, 1, 2, 3 | |
| PM_BR_UNCOND_CMPL | IFU | 0, 1, 2, 3 | |
| PM_CASTOUT_ISSUED | Castouts issued | 0, 1, 2, 3 | |
| PM_CASTOUT_ISSUED_GPR | Castouts issued GPR | 0, 1, 2, 3 | |
| PM_CHIP_PUMP_CPRED | Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for all data types ( demand load,data,inst prefetch,inst fetch,xlate (I or d). | 0 | |
| PM_CLB_HELD | CLB Hold: Any Reason | 0, 1, 2, 3 | |
| PM_CMPLU_STALL | Completion stall. | 3 | |
| PM_CMPLU_STALL_BRU | Completion stall due to a Branch Unit. | 3 | |
| PM_CMPLU_STALL_BRU_CRU | Completion stall due to IFU. | 1 | |
| PM_CMPLU_STALL_COQ_FULL | Completion stall due to CO q full. | 2 | |
| PM_CMPLU_STALL_DCACHE_MISS | Completion stall by Dcache miss. | 1 | |
| PM_CMPLU_STALL_DMISS_L21_L31 | Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3). | 1 | |
| PM_CMPLU_STALL_DMISS_L2L3 | Completion stall by Dcache miss which resolved in L2/L3. | 1 | |
| PM_CMPLU_STALL_DMISS_L2L3_CONFLICT | Completion stall due to cache miss resolving in core's L2/L3 with a conflict. | 3 | |
| PM_CMPLU_STALL_DMISS_L3MISS | Completion stall due to cache miss resolving missed the L3. | 3 | |
| PM_CMPLU_STALL_DMISS_LMEM | Completion stall due to cache miss resolving in core's Local Memory. | 3 | |
| PM_CMPLU_STALL_DMISS_REMOTE | Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3). | 1 | |
| PM_CMPLU_STALL_ERAT_MISS | Completion stall due to LSU reject ERAT miss. | 3 | |
| PM_CMPLU_STALL_FLUSH | completion stall due to flush by own thread. | 2 | |
| PM_CMPLU_STALL_FXLONG | Completion stall due to a long latency fixed point instruction. | 3 | |
| PM_CMPLU_STALL_FXU | Completion stall due to FXU. | 1 | |
| PM_CMPLU_STALL_HWSYNC | completion stall due to hwsync. | 2 | |
| PM_CMPLU_STALL_LOAD_FINISH | Completion stall due to a Load finish. | 3 | |
| PM_CMPLU_STALL_LSU | Completion stall by LSU instruction. | 1 | |
| PM_CMPLU_STALL_LWSYNC | completion stall due to isync/lwsync. | 0 | |
| PM_CMPLU_STALL_MEM_ECC_DELAY | Completion stall due to mem ECC delay. | 2 | |
| PM_CMPLU_STALL_NO_NTF | Completion stall due to nop. | 1 | |
| PM_CMPLU_STALL_NTCG_FLUSH | Completion stall due to reject (load hit store). | 1 | |
| PM_CMPLU_STALL_OTHER_CMPL | Instructions core completed while this thread was stalled. | 2 | |
| PM_CMPLU_STALL_REJECT | Completion stall due to LSU reject. | 3 | |
| PM_CMPLU_STALL_REJECT_LHS | Completion stall due to reject (load hit store). | 1 | |
| PM_CMPLU_STALL_REJ_LMQ_FULL | Completion stall due to LSU reject LMQ full. | 3 | |
| PM_CMPLU_STALL_SCALAR | Completion stall due to VSU scalar instruction. | 3 | |
| PM_CMPLU_STALL_SCALAR_LONG | Completion stall due to VSU scalar long latency instruction. | 1 | |
| PM_CMPLU_STALL_STORE | Completion stall by stores. | 1 | |
| PM_CMPLU_STALL_ST_FWD | Completion stall due to store forward. | 3 | |
| PM_CMPLU_STALL_THRD | Completion stall due to thread conflict. | 0 | |
| PM_CMPLU_STALL_VECTOR | Completion stall due to VSU vector instruction. | 1 | |
| PM_CMPLU_STALL_VECTOR_LONG | Completion stall due to VSU vector long instruction. | 3 | |
| PM_CMPLU_STALL_VSU | Completion stall due to VSU instruction. | 1 | |
| PM_CO0_ALLOC | 0.0 | 0 | |
| PM_CO0_BUSY | CO mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point) | 0 | |
| PM_CO_USAGE | Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 CO machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running | 2 | |
| PM_CRU_FIN | IFU Finished a (non-branch) instruction. | 3 | |
| PM_DATA_ALL_CHIP_PUMP_CPRED | Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for a demand load | 0 | |
| PM_DATA_ALL_FROM_DL2L3_MOD | The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 3 | |
| PM_DATA_ALL_FROM_DL2L3_SHR | The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 2 | |
| PM_DATA_ALL_FROM_DL4 | The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 2 | |
| PM_DATA_ALL_FROM_DMEM | The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 3 | |
| PM_DATA_ALL_FROM_L2 | The processor's data cache was reloaded from local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 0 | |
| PM_DATA_ALL_FROM_L21_MOD | The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 3 | |
| PM_DATA_ALL_FROM_L21_SHR | The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 2 | |
| PM_DATA_ALL_FROM_L2MISS_MOD | The processor's data cache was reloaded from a localtion other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 0 | |
| PM_DATA_ALL_FROM_L2_DISP_CONFLICT_LDHITST | The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 2 | |
| PM_DATA_ALL_FROM_L2_DISP_CONFLICT_OTHER | The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 3 | |
| PM_DATA_ALL_FROM_L2_MEPF | The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 1 | |
| PM_DATA_ALL_FROM_L2_NO_CONFLICT | The processor's data cache was reloaded from local core's L2 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 0 | |
| PM_DATA_ALL_FROM_L3 | The processor's data cache was reloaded from local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 3 | |
| PM_DATA_ALL_FROM_L31_ECO_MOD | The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 3 | |
| PM_DATA_ALL_FROM_L31_ECO_SHR | The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 2 | |
| PM_DATA_ALL_FROM_L31_MOD | The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 1 | |
| PM_DATA_ALL_FROM_L31_SHR | The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 0 | |
| PM_DATA_ALL_FROM_L3MISS_MOD | The processor's data cache was reloaded from a localtion other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 3 | |
| PM_DATA_ALL_FROM_L3_DISP_CONFLICT | The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 2 | |
| PM_DATA_ALL_FROM_L3_MEPF | The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 1 | |
| PM_DATA_ALL_FROM_L3_NO_CONFLICT | The processor's data cache was reloaded from local core's L3 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 0 | |
| PM_DATA_ALL_FROM_LL4 | The processor's data cache was reloaded from the local chip's L4 cache due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 0 | |
| PM_DATA_ALL_FROM_LMEM | The processor's data cache was reloaded from the local chip's Memory due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 1 | |
| PM_DATA_ALL_FROM_MEMORY | The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 1 | |
| PM_DATA_ALL_FROM_OFF_CHIP_CACHE | The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 3 | |
| PM_DATA_ALL_FROM_ON_CHIP_CACHE | The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 0 | |
| PM_DATA_ALL_FROM_RL2L3_MOD | The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 1 | |
| PM_DATA_ALL_FROM_RL2L3_SHR | The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 0 | |
| PM_DATA_ALL_FROM_RL4 | The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 1 | |
| PM_DATA_ALL_FROM_RMEM | The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 | 2 | |
| PM_DATA_ALL_GRP_PUMP_CPRED | Initial and Final Pump Scope and data sourced across this scope was group pump for a demand load | 1 | |
| PM_DATA_ALL_GRP_PUMP_MPRED | got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro | 1 | Final Pump ScopeGroup to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) |
| PM_DATA_ALL_GRP_PUMP_MPRED_RTY | to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor a demand load | 0 | Final Pump ScopeGroup |
| PM_DATA_ALL_PUMP_CPRED | Pump prediction correct. Counts across all types of pumps for a demand load | 0 | |
| PM_DATA_ALL_PUMP_MPRED | Pump Mis prediction Counts across all types of pumpsfor a demand load | 3 | |
| PM_DATA_ALL_SYS_PUMP_CPRED | Initial and Final Pump Scope and data sourced across this scope was system pump for a demand load | 2 | |
| PM_DATA_ALL_SYS_PUMP_MPRED | Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or | 2 | |
| PM_DATA_ALL_SYS_PUMP_MPRED_RTY | Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for a demand load | 3 | |
| PM_DATA_CHIP_PUMP_CPRED | Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for a demand load. | 0 | |
| PM_DATA_FROM_DL2L3_MOD | The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 3 | |
| PM_DATA_FROM_DL2L3_SHR | The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 2 | |
| PM_DATA_FROM_DL4 | The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 2 | |
| PM_DATA_FROM_DMEM | The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 3 | |
| PM_DATA_FROM_L2 | The processor's data cache was reloaded from local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 0 | |
| PM_DATA_FROM_L21_MOD | The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 3 | |
| PM_DATA_FROM_L21_SHR | The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 2 | |
| PM_DATA_FROM_L2MISS_MOD | The processor's data cache was reloaded from a localtion other than the local core's L2 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 0 | |
| PM_DATA_FROM_L2_DISP_CONFLICT_LDHITST | The processor's data cache was reloaded from local core's L2 with load hit store conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 2 | |
| PM_DATA_FROM_L2_DISP_CONFLICT_OTHER | The processor's data cache was reloaded from local core's L2 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 3 | |
| PM_DATA_FROM_L2_MEPF | The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 1 | |
| PM_DATA_FROM_L2_NO_CONFLICT | The processor's data cache was reloaded from local core's L2 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1 . | 0 | |
| PM_DATA_FROM_L3 | The processor's data cache was reloaded from local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 3 | |
| PM_DATA_FROM_L31_ECO_MOD | The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 3 | |
| PM_DATA_FROM_L31_ECO_SHR | The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 2 | |
| PM_DATA_FROM_L31_MOD | The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 1 | |
| PM_DATA_FROM_L31_SHR | The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 0 | |
| PM_DATA_FROM_L3MISS_MOD | The processor's data cache was reloaded from a localtion other than the local core's L3 due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 3 | |
| PM_DATA_FROM_L3_DISP_CONFLICT | The processor's data cache was reloaded from local core's L3 with dispatch conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 2 | |
| PM_DATA_FROM_L3_MEPF | The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 1 | |
| PM_DATA_FROM_L3_NO_CONFLICT | The processor's data cache was reloaded from local core's L3 without conflict due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 0 | |
| PM_DATA_FROM_LL4 | The processor's data cache was reloaded from the local chip's L4 cache due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 0 | |
| PM_DATA_FROM_LMEM | The processor's data cache was reloaded from the local chip's Memory due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 1 | |
| PM_DATA_FROM_MEMORY | The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 1 | |
| PM_DATA_FROM_OFF_CHIP_CACHE | The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 3 | |
| PM_DATA_FROM_ON_CHIP_CACHE | The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 0 | |
| PM_DATA_FROM_RL2L3_MOD | The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 1 | |
| PM_DATA_FROM_RL2L3_SHR | The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 0 | |
| PM_DATA_FROM_RL4 | The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 1 | |
| PM_DATA_FROM_RMEM | The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either only demand loads or demand loads plus prefetches if MMCR1[16] is 1. | 2 | |
| PM_DATA_GRP_PUMP_CPRED | Initial and Final Pump Scope and data sourced across this scope was group pump for a demand load. | 1 | |
| PM_DATA_GRP_PUMP_MPRED | got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro | 1 | Final Pump ScopeGroup to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) |
| PM_DATA_GRP_PUMP_MPRED_RTY | to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor a demand load. | 0 | Final Pump ScopeGroup |
| PM_DATA_PUMP_CPRED | Pump prediction correct. Counts across all types of pumps for a demand load. | 0 | |
| PM_DATA_PUMP_MPRED | Pump Mis prediction Counts across all types of pumpsfor a demand load. | 3 | |
| PM_DATA_SYS_PUMP_CPRED | Initial and Final Pump Scope and data sourced across this scope was system pump for a demand load. | 2 | |
| PM_DATA_SYS_PUMP_MPRED | Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or | 2 | |
| PM_DATA_SYS_PUMP_MPRED_RTY | Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for a demand load. | 3 | |
| PM_DATA_TABLEWALK_CYC | Data Tablewalk Active. | 2 | |
| PM_DC_COLLISIONS | DATA Cache collisions42 | 0, 1, 2, 3 | |
| PM_DC_PREF_STREAM_ALLOC | Stream marked valid. The stream could have been allocated through the hardware prefetch mechanism or through software. This is combined ls0 and ls1. | 0 | |
| PM_DC_PREF_STREAM_CONF | A demand load referenced a line in an active prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software. Combine up + down. | 1 | |
| PM_DC_PREF_STREAM_FUZZY_CONF | A demand load referenced a line in an active fuzzy prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.Fuzzy stream confirm (out of order effects, or pf cant keep up). | 3 | |
| PM_DC_PREF_STREAM_STRIDED_CONF | A demand load referenced a line in an active strided prefetch stream. The stream could have been allocated through the hardware prefetch mechanism or through software.. | 2 | |
| PM_DERAT_MISS_16G | Data ERAT Miss (Data TLB Access) page size 16G. | 3 | |
| PM_DERAT_MISS_16M | Data ERAT Miss (Data TLB Access) page size 16M. | 2 | |
| PM_DERAT_MISS_4K | Data ERAT Miss (Data TLB Access) page size 4K. | 0 | |
| PM_DERAT_MISS_64K | Data ERAT Miss (Data TLB Access) page size 64K. | 1 | |
| PM_DFU | Finish DFU (all finish) | 0, 1, 2, 3 | |
| PM_DFU_DCFFIX | Convert from fixed opcode finish (dcffix,dcffixq) | 0, 1, 2, 3 | |
| PM_DFU_DENBCD | BCD->DPD opcode finish (denbcd, denbcdq) | 0, 1, 2, 3 | |
| PM_DFU_MC | Finish DFU multicycle | 0, 1, 2, 3 | |
| PM_DISP_CLB_HELD_BAL | Dispatch/CLB Hold: Balance | 0, 1, 2, 3 | |
| PM_DISP_CLB_HELD_RES | Dispatch/CLB Hold: Resource | 0, 1, 2, 3 | |
| PM_DISP_CLB_HELD_SB | Dispatch/CLB Hold: Scoreboard | 0, 1, 2, 3 | |
| PM_DISP_CLB_HELD_SYNC | Dispatch/CLB Hold: Sync type instruction | 0, 1, 2, 3 | |
| PM_DISP_CLB_HELD_TLBIE | Dispatch Hold: Due to TLBIE | 0, 1, 2, 3 | |
| PM_DISP_HELD | Dispatch Held. | 0 | |
| PM_DISP_HELD_IQ_FULL | Dispatch held due to Issue q full. | 1 | |
| PM_DISP_HELD_MAP_FULL | Dispatch held due to Mapper full. | 0 | |
| PM_DISP_HELD_SRQ_FULL | Dispatch held due SRQ no room. | 2 | |
| PM_DISP_HELD_SYNC_HOLD | Dispatch held due to SYNC hold. | 3 | |
| PM_DISP_HOLD_GCT_FULL | Dispatch Hold Due to no space in the GCT | 0, 1, 2, 3 | |
| PM_DISP_WT | Dispatched Starved (not held, nothing to dispatch). | 2 | |
| PM_DPTEG_FROM_DL2L3_MOD | A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. | 3 | |
| PM_DPTEG_FROM_DL2L3_SHR | A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request. | 2 | |
| PM_DPTEG_FROM_DL4 | A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a data side request. | 2 | |
| PM_DPTEG_FROM_DMEM | A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a data side request. | 3 | |
| PM_DPTEG_FROM_L2 | A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request. | 0 | |
| PM_DPTEG_FROM_L21_MOD | A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a data side request. | 3 | |
| PM_DPTEG_FROM_L21_SHR | A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a data side request. | 2 | |
| PM_DPTEG_FROM_L2MISS | A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a data side request. | 0 | |
| PM_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST | A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a data side request. | 2 | |
| PM_DPTEG_FROM_L2_DISP_CONFLICT_OTHER | A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a data side request. | 3 | |
| PM_DPTEG_FROM_L2_MEPF | A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request. | 1 | |
| PM_DPTEG_FROM_L2_NO_CONFLICT | A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request. | 0 | |
| PM_DPTEG_FROM_L3 | A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request. | 3 | |
| PM_DPTEG_FROM_L31_ECO_MOD | A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a data side request. | 3 | |
| PM_DPTEG_FROM_L31_ECO_SHR | A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side request. | 2 | |
| PM_DPTEG_FROM_L31_MOD | A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a data side request. | 1 | |
| PM_DPTEG_FROM_L31_SHR | A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side request. | 0 | |
| PM_DPTEG_FROM_L3MISS | A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a data side request. | 3 | |
| PM_DPTEG_FROM_L3_DISP_CONFLICT | A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request. | 2 | |
| PM_DPTEG_FROM_L3_MEPF | A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request. | 1 | |
| PM_DPTEG_FROM_L3_NO_CONFLICT | A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request. | 0 | |
| PM_DPTEG_FROM_LL4 | A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. | 0 | |
| PM_DPTEG_FROM_LMEM | A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request. | 1 | |
| PM_DPTEG_FROM_MEMORY | A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. | 1 | |
| PM_DPTEG_FROM_OFF_CHIP_CACHE | A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request. | 3 | |
| PM_DPTEG_FROM_ON_CHIP_CACHE | A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request. | 0 | |
| PM_DPTEG_FROM_RL2L3_MOD | A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. | 1 | |
| PM_DPTEG_FROM_RL2L3_SHR | A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request. | 0 | |
| PM_DPTEG_FROM_RL4 | A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request. | 1 | |
| PM_DPTEG_FROM_RMEM | A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a data side request. | 2 | |
| PM_DSLB_MISS | Data SLB Miss - Total of all segment sizesData SLB misses | 0, 1, 2, 3 | |
| PM_DTLB_MISS_16G | Data TLB Miss page size 16G. | 0 | |
| PM_DTLB_MISS_16M | Data TLB Miss page size 16M. | 3 | |
| PM_DTLB_MISS_4K | Data TLB Miss page size 4k. | 1 | |
| PM_DTLB_MISS_64K | Data TLB Miss page size 64K. | 2 | |
| PM_EAT_FORCE_MISPRED | XL-form branch was mispredicted due to the predicted target address missing from EAT. The EAT forces a mispredict in this case since there is no predicated target to validate. This is a rare case that may occur when the EAT is full and a branch is | 0, 1, 2, 3 | |
| PM_EAT_FULL_CYC | Cycles No room in EATSet on bank conflict and case where no ibuffers available. | 0, 1, 2, 3 | |
| PM_EE_OFF_EXT_INT | Ee off and external interrupt | 0, 1, 2, 3 | |
| PM_FAV_TBEGIN | Dispatch time Favored tbegin | 0, 1, 2, 3 | |
| PM_FLOP_SUM_SCALAR | flops summary scalar instructions | 0, 1, 2, 3 | |
| PM_FLOP_SUM_VEC | flops summary vector instructions | 0, 1, 2, 3 | |
| PM_FLUSH_BR_MPRED | Flush caused by branch mispredict | 0, 1, 2, 3 | |
| PM_FLUSH_COMPLETION | Completion Flush. | 2 | |
| PM_FLUSH_DISP | Dispatch flush | 0, 1, 2, 3 | |
| PM_FLUSH_DISP_SB | Dispatch Flush: Scoreboard | 0, 1, 2, 3 | |
| PM_FLUSH_DISP_SYNC | Dispatch Flush: Sync | 0, 1, 2, 3 | |
| PM_FLUSH_DISP_TLBIE | Dispatch Flush: TLBIE | 0, 1, 2, 3 | |
| PM_FLUSH_LSU | Flush initiated by LSU | 0, 1, 2, 3 | |
| PM_FLUSH_PARTIAL | Partial flush | 0, 1, 2, 3 | |
| PM_FPU0_FCONV | Convert instruction executed | 0, 1, 2, 3 | |
| PM_FPU0_FEST | Estimate instruction executed | 0, 1, 2, 3 | |
| PM_FPU0_FRSP | Round to single precision instruction executed | 0, 1, 2, 3 | |
| PM_FPU1_FCONV | Convert instruction executed | 0, 1, 2, 3 | |
| PM_FPU1_FEST | Estimate instruction executed | 0, 1, 2, 3 | |
| PM_FPU1_FRSP | Round to single precision instruction executed | 0, 1, 2, 3 | |
| PM_FREQ_DOWN | Frequency is being slewed down due to Power Management. | 2 | |
| PM_FREQ_UP | Frequency is being slewed up due to Power Management. | 3 | |
| PM_FUSION_TOC_GRP0_1 | One pair of instructions fused with TOC in Group0 | 0, 1, 2, 3 | |
| PM_FUSION_TOC_GRP0_2 | Two pairs of instructions fused with TOCin Group0 | 0, 1, 2, 3 | |
| PM_FUSION_TOC_GRP0_3 | Three pairs of instructions fused with TOC in Group0 | 0, 1, 2, 3 | |
| PM_FUSION_TOC_GRP1_1 | One pair of instructions fused with TOX in Group1 | 0, 1, 2, 3 | |
| PM_FUSION_VSX_GRP0_1 | One pair of instructions fused with VSX in Group0 | 0, 1, 2, 3 | |
| PM_FUSION_VSX_GRP0_2 | Two pairs of instructions fused with VSX in Group0 | 0, 1, 2, 3 | |
| PM_FUSION_VSX_GRP0_3 | Three pairs of instructions fused with VSX in Group0 | 0, 1, 2, 3 | |
| PM_FUSION_VSX_GRP1_1 | One pair of instructions fused with VSX in Group1 | 0, 1, 2, 3 | |
| PM_FXU0_BUSY_FXU1_IDLE | fxu0 busy and fxu1 idle. | 2 | |
| PM_FXU0_FIN | FXU0 Finished. | 0 | |
| PM_FXU1_BUSY_FXU0_IDLE | fxu0 idle and fxu1 busy. . | 3 | |
| PM_FXU1_FIN | FXU1 Finished. | 3 | |
| PM_FXU_BUSY | fxu0 busy and fxu1 busy.. | 1 | |
| PM_FXU_IDLE | fxu0 idle and fxu1 idle. | 0 | |
| PM_GCT_EMPTY_CYC | No itags assigned either thread (GCT Empty). | 1 | |
| PM_GCT_MERGE | Group dispatched on a merged GCT empty. GCT entries can be merged only within the same thread | 0, 1, 2, 3 | |
| PM_GCT_NOSLOT_BR_MPRED | Gct empty for this thread due to branch mispred. | 3 | |
| PM_GCT_NOSLOT_BR_MPRED_ICMISS | Gct empty for this thread due to Icache Miss and branch mispred. | 3 | |
| PM_GCT_NOSLOT_DISP_HELD_ISSQ | Gct empty for this thread due to dispatch hold on this thread due to Issue q full. | 1 | |
| PM_GCT_NOSLOT_DISP_HELD_MAP | Gct empty for this thread due to dispatch hold on this thread due to Mapper full. | 3 | |
| PM_GCT_NOSLOT_DISP_HELD_OTHER | Gct empty for this thread due to dispatch hold on this thread due to sync. | 1 | |
| PM_GCT_NOSLOT_DISP_HELD_SRQ | Gct empty for this thread due to dispatch hold on this thread due to SRQ full. | 1 | |
| PM_GCT_NOSLOT_IC_L3MISS | Gct empty for this thread due to icach l3 miss. | 3 | |
| PM_GCT_NOSLOT_IC_MISS | Gct empty for this thread due to Icache Miss. | 1 | |
| PM_GCT_UTIL_11_14_ENTRIES | GCT Utilization 11-14 entries | 0, 1, 2, 3 | |
| PM_GCT_UTIL_15_17_ENTRIES | GCT Utilization 15-17 entries | 0, 1, 2, 3 | |
| PM_GCT_UTIL_18_ENTRIES | GCT Utilization 18+ entries | 0, 1, 2, 3 | |
| PM_GCT_UTIL_1_2_ENTRIES | GCT Utilization 1-2 entries | 0, 1, 2, 3 | |
| PM_GCT_UTIL_3_6_ENTRIES | GCT Utilization 3-6 entries | 0, 1, 2, 3 | |
| PM_GCT_UTIL_7_10_ENTRIES | GCT Utilization 7-10 entries | 0, 1, 2, 3 | |
| PM_GRP_BR_MPRED_NONSPEC | Group experienced Non-speculative br mispredicct. | 0 | |
| PM_GRP_CMPL | group completed. | 2 | |
| PM_GRP_DISP | . | 2 | dispatch_success Group Dispatched |
| PM_GRP_IC_MISS_NONSPEC | Group experi enced Non-specu lative I cache miss. | 0 | |
| PM_GRP_MRK | Instruction marked in idu. | 0 | |
| PM_GRP_NON_FULL_GROUP | GROUPs where we did not have 6 non branch instructions in the group(ST mode), in SMT mode 3 non branches | 0, 1, 2, 3 | |
| PM_GRP_PUMP_CPRED | Initial and Final Pump Scope and data sourced across this scope was group pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate). | 1 | |
| PM_GRP_PUMP_MPRED | got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro | 1 | Final Pump ScopeGroup to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) |
| PM_GRP_PUMP_MPRED_RTY | to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate). | 0 | Final Pump ScopeGroup |
| PM_GRP_TERM_2ND_BRANCH | There were enough instructions in the Ibuffer, but 2nd branch ends group | 0, 1, 2, 3 | |
| PM_GRP_TERM_FPU_AFTER_BR | There were enough instructions in the Ibuffer, but FPU OP IN same group after a branch terminates a group, cant do partial flushes | 0, 1, 2, 3 | |
| PM_GRP_TERM_NOINST | Do not fill every slot in the group, Not enough instructions in the Ibuffer. This includes cases where the group started with enough instructions, but some got knocked out by a cache miss or branch redirect (which would also empty the Ibuffer). | 0, 1, 2, 3 | |
| PM_GRP_TERM_OTHER | There were enough instructions in the Ibuffer, but the group terminated early for some other reason, most likely due to a First or Last. | 0, 1, 2, 3 | |
| PM_GRP_TERM_SLOT_LIMIT | There were enough instructions in the Ibuffer, but 3 src RA/RB/RC , 2 way crack caused a group termination | 0, 1, 2, 3 | |
| PM_HV_CYC | cycles in hypervisor mode . | 1 | |
| PM_IBUF_FULL_CYC | Cycles No room in ibufffully qualified tranfer (if5 valid). | 0, 1, 2, 3 | |
| PM_IC_DEMAND_CYC | Demand ifetch pending. | 0 | |
| PM_IC_DEMAND_L2_BHT_REDIRECT | L2 I cache demand request due to BHT redirect, branch redirect ( 2 bubbles 3 cycles) | 0, 1, 2, 3 | |
| PM_IC_DEMAND_L2_BR_REDIRECT | L2 I cache demand request due to branch Mispredict ( 15 cycle path) | 0, 1, 2, 3 | |
| PM_IC_DEMAND_REQ | Demand Instruction fetch request | 0, 1, 2, 3 | |
| PM_IC_INVALIDATE | Ic line invalidated | 0, 1, 2, 3 | |
| PM_IC_PREF_CANCEL_HIT | Prefetch Canceled due to icache hit | 0, 1, 2, 3 | |
| PM_IC_PREF_CANCEL_L2 | L2 Squashed request | 0, 1, 2, 3 | |
| PM_IC_PREF_CANCEL_PAGE | Prefetch Canceled due to page boundary | 0, 1, 2, 3 | |
| PM_IC_PREF_REQ | Instruction prefetch requests | 0, 1, 2, 3 | |
| PM_IC_PREF_WRITE | Instruction prefetch written into IL1 | 0, 1, 2, 3 | |
| PM_IC_RELOAD_PRIVATE | Reloading line was brought in private for a specific thread. Most lines are brought in shared for all eight thrreads. If RA does not match then invalidates and then brings it shared to other thread. In P7 line brought in private , then line was inv | 0, 1, 2, 3 | |
| PM_IERAT_RELOAD_16M | IERAT Reloaded (Miss) for a 16M page. | 3 | |
| PM_IERAT_RELOAD_4K | IERAT Reloaded (Miss) for a 4k page. | 1 | |
| PM_IERAT_RELOAD_64K | IERAT Reloaded (Miss) for a 64k page. | 2 | |
| PM_IFETCH_THROTTLE | Cycles instruction fecth was throttled in IFU. | 2 | |
| PM_IFU_L2_TOUCH | L2 touch to update MRU on a line | 0, 1, 2, 3 | |
| PM_INST_ALL_CHIP_PUMP_CPRED | Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch | 0 | |
| PM_INST_ALL_FROM_DL2L3_MOD | The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 3 | |
| PM_INST_ALL_FROM_DL2L3_SHR | The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 2 | |
| PM_INST_ALL_FROM_DL4 | The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 2 | |
| PM_INST_ALL_FROM_DMEM | The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 3 | |
| PM_INST_ALL_FROM_L2 | The processor's Instruction cache was reloaded from local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 0 | |
| PM_INST_ALL_FROM_L21_MOD | The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 3 | |
| PM_INST_ALL_FROM_L21_SHR | The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 2 | |
| PM_INST_ALL_FROM_L2MISS | The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 0 | |
| PM_INST_ALL_FROM_L2_DISP_CONFLICT_LDHITST | The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 2 | |
| PM_INST_ALL_FROM_L2_DISP_CONFLICT_OTHER | The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 3 | |
| PM_INST_ALL_FROM_L2_MEPF | The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 1 | |
| PM_INST_ALL_FROM_L2_NO_CONFLICT | The processor's Instruction cache was reloaded from local core's L2 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 0 | |
| PM_INST_ALL_FROM_L3 | The processor's Instruction cache was reloaded from local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 3 | |
| PM_INST_ALL_FROM_L31_ECO_MOD | The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 3 | |
| PM_INST_ALL_FROM_L31_ECO_SHR | The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 2 | |
| PM_INST_ALL_FROM_L31_MOD | The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 1 | |
| PM_INST_ALL_FROM_L31_SHR | The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 0 | |
| PM_INST_ALL_FROM_L3MISS_MOD | The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 3 | |
| PM_INST_ALL_FROM_L3_DISP_CONFLICT | The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 2 | |
| PM_INST_ALL_FROM_L3_MEPF | The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 1 | |
| PM_INST_ALL_FROM_L3_NO_CONFLICT | The processor's Instruction cache was reloaded from local core's L3 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 0 | |
| PM_INST_ALL_FROM_LL4 | The processor's Instruction cache was reloaded from the local chip's L4 cache due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 0 | |
| PM_INST_ALL_FROM_LMEM | The processor's Instruction cache was reloaded from the local chip's Memory due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 1 | |
| PM_INST_ALL_FROM_MEMORY | The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 1 | |
| PM_INST_ALL_FROM_OFF_CHIP_CACHE | The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 3 | |
| PM_INST_ALL_FROM_ON_CHIP_CACHE | The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 0 | |
| PM_INST_ALL_FROM_RL2L3_MOD | The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 1 | |
| PM_INST_ALL_FROM_RL2L3_SHR | The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 0 | |
| PM_INST_ALL_FROM_RL4 | The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 1 | |
| PM_INST_ALL_FROM_RMEM | The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 | 2 | |
| PM_INST_ALL_GRP_PUMP_CPRED | Initial and Final Pump Scope and data sourced across this scope was group pump for an instruction fetch | 1 | |
| PM_INST_ALL_GRP_PUMP_MPRED | got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro | 1 | Final Pump ScopeGroup to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) |
| PM_INST_ALL_GRP_PUMP_MPRED_RTY | to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor an instruction fetch | 0 | Final Pump ScopeGroup |
| PM_INST_ALL_PUMP_CPRED | Pump prediction correct. Counts across all types of pumpsfor an instruction fetch | 0 | |
| PM_INST_ALL_PUMP_MPRED | Pump Mis prediction Counts across all types of pumpsfor an instruction fetch | 3 | |
| PM_INST_ALL_SYS_PUMP_CPRED | Initial and Final Pump Scope and data sourced across this scope was system pump for an instruction fetch | 2 | |
| PM_INST_ALL_SYS_PUMP_MPRED | Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or | 2 | |
| PM_INST_ALL_SYS_PUMP_MPRED_RTY | Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for an instruction fetch | 3 | |
| PM_INST_CHIP_PUMP_CPRED | Initial and Final Pump Scope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch. | 0 | |
| PM_INST_CMPL | PPC Instructions Finished (completed). | 0, 1, 2, 3 | |
| PM_INST_FROM_DL2L3_MOD | The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 3 | |
| PM_INST_FROM_DL2L3_SHR | The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 2 | |
| PM_INST_FROM_DL4 | The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 2 | |
| PM_INST_FROM_DMEM | The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group (Distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 3 | |
| PM_INST_FROM_L1 | Instruction fetches from L1 | 0, 1, 2, 3 | |
| PM_INST_FROM_L2 | The processor's Instruction cache was reloaded from local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 0 | |
| PM_INST_FROM_L21_MOD | The processor's Instruction cache was reloaded with Modified (M) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 3 | |
| PM_INST_FROM_L21_SHR | The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 2 | |
| PM_INST_FROM_L2MISS | The processor's Instruction cache was reloaded from a localtion other than the local core's L2 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 0 | |
| PM_INST_FROM_L2_DISP_CONFLICT_LDHITST | The processor's Instruction cache was reloaded from local core's L2 with load hit store conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 2 | |
| PM_INST_FROM_L2_DISP_CONFLICT_OTHER | The processor's Instruction cache was reloaded from local core's L2 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 3 | |
| PM_INST_FROM_L2_MEPF | The processor's Instruction cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 1 | |
| PM_INST_FROM_L2_NO_CONFLICT | The processor's Instruction cache was reloaded from local core's L2 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 0 | |
| PM_INST_FROM_L3 | The processor's Instruction cache was reloaded from local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 3 | |
| PM_INST_FROM_L31_ECO_MOD | The processor's Instruction cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 3 | |
| PM_INST_FROM_L31_ECO_SHR | The processor's Instruction cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 2 | |
| PM_INST_FROM_L31_MOD | The processor's Instruction cache was reloaded with Modified (M) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 1 | |
| PM_INST_FROM_L31_SHR | The processor's Instruction cache was reloaded with Shared (S) data from another core's L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 0 | |
| PM_INST_FROM_L3MISS_MOD | The processor's Instruction cache was reloaded from a localtion other than the local core's L3 due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 3 | |
| PM_INST_FROM_L3_DISP_CONFLICT | The processor's Instruction cache was reloaded from local core's L3 with dispatch conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 2 | |
| PM_INST_FROM_L3_MEPF | The processor's Instruction cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 1 | |
| PM_INST_FROM_L3_NO_CONFLICT | The processor's Instruction cache was reloaded from local core's L3 without conflict due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 0 | |
| PM_INST_FROM_LL4 | The processor's Instruction cache was reloaded from the local chip's L4 cache due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 0 | |
| PM_INST_FROM_LMEM | The processor's Instruction cache was reloaded from the local chip's Memory due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 1 | |
| PM_INST_FROM_MEMORY | The processor's Instruction cache was reloaded from a memory location including L4 from local remote or distant due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 1 | |
| PM_INST_FROM_OFF_CHIP_CACHE | The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 3 | |
| PM_INST_FROM_ON_CHIP_CACHE | The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 0 | |
| PM_INST_FROM_RL2L3_MOD | The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 1 | |
| PM_INST_FROM_RL2L3_SHR | The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 0 | |
| PM_INST_FROM_RL4 | The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 1 | |
| PM_INST_FROM_RMEM | The processor's Instruction cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to either an instruction fetch or instruction fetch plus prefetch if MMCR1[17] is 1 . | 2 | |
| PM_INST_GRP_PUMP_CPRED | Initial and Final Pump Scope and data sourced across this scope was group pump for an instruction fetch. | 1 | |
| PM_INST_GRP_PUMP_MPRED | got data from source that was at smaller scope(Chip) Final pump was group pump and initial pump was chip or final and initial pump was gro | 1 | Final Pump ScopeGroup to get data sourced, ended up larger than Initial Pump Scope OR Final Pump Scope(Group) |
| PM_INST_GRP_PUMP_MPRED_RTY | to get data sourced, ended up larger than Initial Pump Scope (Chip) Final pump was group pump and initial pump was chip pumpfor an instruction fetch. | 0 | Final Pump ScopeGroup |
| PM_INST_IMC_MATCH_CMPL | IMC Match Count. | 0 | |
| PM_INST_IMC_MATCH_DISP | IMC Matches dispatched. | 2 | |
| PM_INST_PUMP_CPRED | Pump prediction correct. Counts across all types of pumpsfor an instruction fetch. | 0 | |
| PM_INST_PUMP_MPRED | Pump Mis prediction Counts across all types of pumpsfor an instruction fetch. | 3 | |
| PM_INST_SYS_PUMP_CPRED | Initial and Final Pump Scope and data sourced across this scope was system pump for an instruction fetch. | 2 | |
| PM_INST_SYS_PUMP_MPRED | Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or | 2 | |
| PM_INST_SYS_PUMP_MPRED_RTY | Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for an instruction fetch. | 3 | |
| PM_IOPS_CMPL | IOPS Completed. | 0 | |
| PM_IOPS_DISP | IOPS dispatched. | 2 | |
| PM_IPTEG_FROM_DL2L3_MOD | A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request. | 3 | |
| PM_IPTEG_FROM_DL2L3_SHR | A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a instruction side request. | 2 | |
| PM_IPTEG_FROM_DL4 | A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a instruction side request. | 2 | |
| PM_IPTEG_FROM_DMEM | A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a instruction side request. | 3 | |
| PM_IPTEG_FROM_L2 | A Page Table Entry was loaded into the TLB from local core's L2 due to a instruction side request. | 0 | |
| PM_IPTEG_FROM_L21_MOD | A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a instruction side request. | 3 | |
| PM_IPTEG_FROM_L21_SHR | A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a instruction side request. | 2 | |
| PM_IPTEG_FROM_L2MISS | A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a instruction side request. | 0 | |
| PM_IPTEG_FROM_L2_DISP_CONFLICT_LDHITST | A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a instruction side request. | 2 | |
| PM_IPTEG_FROM_L2_DISP_CONFLICT_OTHER | A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a instruction side request. | 3 | |
| PM_IPTEG_FROM_L2_MEPF | A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a instruction side request. | 1 | |
| PM_IPTEG_FROM_L2_NO_CONFLICT | A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a instruction side request. | 0 | |
| PM_IPTEG_FROM_L3 | A Page Table Entry was loaded into the TLB from local core's L3 due to a instruction side request. | 3 | |
| PM_IPTEG_FROM_L31_ECO_MOD | A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a instruction side request. | 3 | |
| PM_IPTEG_FROM_L31_ECO_SHR | A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a instruction side request. | 2 | |
| PM_IPTEG_FROM_L31_MOD | A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a instruction side request. | 1 | |
| PM_IPTEG_FROM_L31_SHR | A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a instruction side request. | 0 | |
| PM_IPTEG_FROM_L3MISS | A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a instruction side request. | 3 | |
| PM_IPTEG_FROM_L3_DISP_CONFLICT | A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a instruction side request. | 2 | |
| PM_IPTEG_FROM_L3_MEPF | A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a instruction side request. | 1 | |
| PM_IPTEG_FROM_L3_NO_CONFLICT | A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a instruction side request. | 0 | |
| PM_IPTEG_FROM_LL4 | A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a instruction side request. | 0 | |
| PM_IPTEG_FROM_LMEM | A Page Table Entry was loaded into the TLB from the local chip's Memory due to a instruction side request. | 1 | |
| PM_IPTEG_FROM_MEMORY | A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a instruction side request. | 1 | |
| PM_IPTEG_FROM_OFF_CHIP_CACHE | A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a instruction side request. | 3 | |
| PM_IPTEG_FROM_ON_CHIP_CACHE | A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a instruction side request. | 0 | |
| PM_IPTEG_FROM_RL2L3_MOD | A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request. | 1 | |
| PM_IPTEG_FROM_RL2L3_SHR | A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request. | 0 | |
| PM_IPTEG_FROM_RL4 | A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request. | 1 | |
| PM_IPTEG_FROM_RMEM | A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a instruction side request. | 2 | |
| PM_ISIDE_L2MEMACC | valid when first beat of data comes in for an i-side fetch where data came from mem(or L4) | 3 | |
| PM_ISLB_MISS | I SLB Miss. | 0, 1, 2, 3 | |
| PM_ISU_REJ_FX0 | FX0 ISU reject | 0, 1, 2, 3 | |
| PM_ISU_REJ_FX1 | FX1 ISU reject | 0, 1, 2, 3 | |
| PM_ISU_REF_FXU | ISU | 0, 1, 2, 3 | |
| PM_ISU_REJ_LS0 | LS0 ISU reject | 0, 1, 2, 3 | |
| PM_ISU_REJ_LS1 | LS1 ISU reject | 0, 1, 2, 3 | |
| PM_ISU_REJ_LS2 | LS2 ISU reject | 0, 1, 2, 3 | |
| PM_ISU_REJ_LS3 | LS3 ISU reject | 0, 1, 2, 3 | |
| PM_ISU_REJECTS_ALL | All isu rejects could be more than 1 per cycle | 0, 1, 2, 3 | |
| PM_ISU_REJECT_RES_NA | ISU reject due to resource not available | 0, 1, 2, 3 | |
| PM_ISU_REJECT_SAR_BYPASS | Reject because of SAR bypass | 0, 1, 2, 3 | |
| PM_ISU_REJECT_SRC_NA | ISU reject due to source not available | 0, 1, 2, 3 | |
| PM_ISU_REJ_VS0 | VS0 ISU reject | 0, 1, 2, 3 | |
| PM_ISU_REJ_VS1 | VS1 ISU reject | 0, 1, 2, 3 | |
| PM_ISU_REJ_VSU | ISU | 0, 1, 2, 3 | |
| PM_ISYNC | Isync count per thread | 0, 1, 2, 3 | |
| PM_L1MISS_LAT_EXC_1024 | Reload latency exceeded 1024 cyc | 2 |
0x67: Thresholdable start/stop for L1 sampled instruction load miss/reload
|
| PM_L1MISS_LAT_EXC_2048 | Reload latency exceeded 2048 cyc | 3 |
0x67: Thresholdable start/stop for L1 sampled instruction load miss/reload
|
| PM_L1MISS_LAT_EXC_256 | Reload latency exceeded 256 cyc | 0 |
0x67: Thresholdable start/stop for L1 sampled instruction load miss/reload
|
| PM_L1MISS_LAT_EXC_32 | Reload latency exceeded 32 cyc | 1 |
0x67: Thresholdable start/stop for L1 sampled instruction load miss/reload
|
| PM_L1PF_L2MEMACC | valid when first beat of data comes in for an L1pref where data came from mem(or L4) | 1 | |
| PM_L1_DCACHE_RELOADED_ALL | L1 data cache reloaded for demand or prefetch . | 0 | |
| PM_L1_DEMAND_WRITE | Instruction Demand sectors wriittent into IL1 | 0, 1, 2, 3 | |
| PM_L1_ICACHE_RELOADED_ALL | Counts all Icache reloads includes demand, prefetchm prefetch turned into demand and demand turned into prefetch. | 3 | |
| PM_L1_ICACHE_RELOADED_PREF | Counts all Icache prefetch reloads ( includes demand turned into prefetch). | 2 | |
| PM_L2_CHIP_PUMP | RC requests that were local on chip pump attempts | 1 | |
| PM_L2_RTY_ST | RC retries on PB for any store from core | 2 | |
| PM_L2_ST | All successful D-side store dispatches for this thread | 0 | |
| PM_L2_ST_MISS | All successful D-side store dispatches for this thread that were L2 Miss | 0 | |
| PM_L2_SYS_PUMP | RC requests that were system pump attempts | 2 | |
| PM_L2_TM_REQ_ABORT | TM abort. | 0 | |
| PM_L2_TM_ST_ABORT_SISTER | TM marked store abort. | 2 | |
| PM_L3_CI_USAGE | rotating sample of 16 CI or CO actives | 0 | |
| PM_L3_CO0_ALLOC | 0.0 | 2 | |
| PM_L3_CO0_BUSY | lifetime, sample of CO machine 0 valid | 2 | |
| PM_L3_CO_L31 | L3 CO to L3.1 OR of port 0 and 1 ( lossy) | 1 | |
| PM_L3_CO_MEM | L3 CO to memory OR of port 0 and 1 ( lossy) | 1 | |
| PM_L3_CO_MEPF | L3 CO of line in Mep state ( includes casthrough) | 0 | |
| PM_L3_LD_PREF | L3 Load Prefetches. | 0 | |
| PM_L3_PF0_ALLOC | 0.0 | 3 | |
| PM_L3_PF0_BUSY | lifetime, sample of PF machine 0 valid | 3 | |
| PM_L3_PF_MISS_L3 | L3 Prefetch missed in L3 | 0 | |
| PM_L3_PF_OFF_CHIP_CACHE | L3 Prefetch from Off chip cache | 2 | |
| PM_L3_PF_OFF_CHIP_MEM | L3 Prefetch from Off chip memory | 3 | |
| PM_L3_PF_ON_CHIP_CACHE | L3 Prefetch from On chip cache | 2 | |
| PM_L3_PF_ON_CHIP_MEM | L3 Prefetch from On chip memory | 3 | |
| PM_L3_PF_USAGE | rotating sample of 32 PF actives | 1 | |
| PM_L3_PREF_ALL | Total HW L3 prefetches(Load+store). | 3 | |
| PM_L3_RD0_ALLOC | 0.0 | 3 | |
| PM_L3_RD0_BUSY | lifetime, sample of RD machine 0 valid | 3 | |
| PM_L3_RD_USAGE | rotating sample of 16 RD actives | 1 | |
| PM_L3_SN0_ALLOC | 0.0 | 2 | |
| PM_L3_SN0_BUSY | lifetime, sample of snooper machine 0 valid | 2 | |
| PM_L3_SN_USAGE | rotating sample of 8 snoop valids | 0 | |
| PM_L3_ST_PREF | L3 store Prefetches. | 1 | |
| PM_L3_SW_PREF | Data stream touchto L3. | 2 | |
| PM_L3_WI0_ALLOC | 0.0 | 0 | |
| PM_LARX_FIN | Larx finished . | 2 | |
| PM_LD_CMPL | count of Loads completed. | 0 | |
| PM_LD_L3MISS_PEND_CYC | Cycles L3 miss was pending for this thread. | 0 | |
| PM_LD_REF_L1 | Load Ref count combined for all units. | 0 | |
| PM_LD_REF_L1_LSU0 | LS0 L1 D cache load references counted at finish, gated by rejectLSU0 L1 D cache load references | 0, 1, 2, 3 | |
| PM_LD_REF_L1_LSU1 | LS1 L1 D cache load references counted at finish, gated by rejectLSU1 L1 D cache load references | 0, 1, 2, 3 | |
| PM_LD_REF_L1_LSU2 | LS2 L1 D cache load references counted at finish, gated by reject42 | 0, 1, 2, 3 | |
| PM_LD_REF_L1_LSU3 | LS3 L1 D cache load references counted at finish, gated by reject42 | 0, 1, 2, 3 | |
| PM_LINK_STACK_INVALID_PTR | A flush were LS ptr is invalid, results in a pop , A lot of interrupts between push and pops | 0, 1, 2, 3 | |
| PM_LINK_STACK_WRONG_ADD_PRED | Link stack predicts wrong address, because of link stack design limitation. | 0, 1, 2, 3 | |
| PM_LS0_ERAT_MISS_PREF | LS0 Erat miss due to prefetch42 | 0, 1, 2, 3 | |
| PM_LS0_L1_PREF | LS0 L1 cache data prefetches42 | 0, 1, 2, 3 | |
| PM_LS0_L1_SW_PREF | Software L1 Prefetches, including SW Transient Prefetches42 | 0, 1, 2, 3 | |
| PM_LS1_ERAT_MISS_PREF | LS1 Erat miss due to prefetch42 | 0, 1, 2, 3 | |
| PM_LS1_L1_PREF | LS1 L1 cache data prefetches42 | 0, 1, 2, 3 | |
| PM_LS1_L1_SW_PREF | Software L1 Prefetches, including SW Transient Prefetches42 | 0, 1, 2, 3 | |
| PM_LSU0_FLUSH_LRQ | LS0 Flush: LRQLSU0 LRQ flushes | 0, 1, 2, 3 | |
| PM_LSU0_FLUSH_SRQ | LS0 Flush: SRQLSU0 SRQ lhs flushes | 0, 1, 2, 3 | |
| PM_LSU0_FLUSH_ULD | LS0 Flush: Unaligned LoadLSU0 unaligned load flushes | 0, 1, 2, 3 | |
| PM_LSU0_FLUSH_UST | LS0 Flush: Unaligned StoreLSU0 unaligned store flushes | 0, 1, 2, 3 | |
| PM_LSU0_L1_CAM_CANCEL | ls0 l1 tm cam cancel42 | 0, 1, 2, 3 | |
| PM_LSU0_LARX_FIN | . | 0 | |
| PM_LSU0_LMQ_LHR_MERGE | LS0 Load Merged with another cacheline request42 | 0, 1, 2, 3 | |
| PM_LSU0_NCLD | LS0 Non-cachable Loads counted at finishLSU0 non-cacheable loads | 0, 1, 2, 3 | |
| PM_LSU0_PRIMARY_ERAT_HIT | Primary ERAT hit42 | 0, 1, 2, 3 | |
| PM_LSU0_REJECT | LSU0 reject . | 0 | |
| PM_LSU0_SRQ_STFWD | LS0 SRQ forwarded data to a loadLSU0 SRQ store forwarded | 0, 1, 2, 3 | |
| PM_LSU0_STORE_REJECT | ls0 store reject42 | 0, 1, 2, 3 | |
| PM_LSU0_TMA_REQ_L2 | addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42 | 0, 1, 2, 3 | |
| PM_LSU0_TM_L1_HIT | Load tm hit in L142 | 0, 1, 2, 3 | |
| PM_LSU0_TM_L1_MISS | Load tm L1 miss42 | 0, 1, 2, 3 | |
| PM_LSU1_FLUSH_LRQ | LS1 Flush: LRQLSU1 LRQ flushes | 0, 1, 2, 3 | |
| PM_LSU1_FLUSH_SRQ | LS1 Flush: SRQLSU1 SRQ lhs flushes | 0, 1, 2, 3 | |
| PM_LSU1_FLUSH_ULD | LS 1 Flush: Unaligned LoadLSU1 unaligned load flushes | 0, 1, 2, 3 | |
| PM_LSU1_FLUSH_UST | LS1 Flush: Unaligned StoreLSU1 unaligned store flushes | 0, 1, 2, 3 | |
| PM_LSU1_L1_CAM_CANCEL | ls1 l1 tm cam cancel42 | 0, 1, 2, 3 | |
| PM_LSU1_LARX_FIN | Larx finished in LSU pipe1. | 1 | |
| PM_LSU1_LMQ_LHR_MERGE | LS1 Load Merge with another cacheline request42 | 0, 1, 2, 3 | |
| PM_LSU1_NCLD | LS1 Non-cachable Loads counted at finishLSU1 non-cacheable loads | 0, 1, 2, 3 | |
| PM_LSU1_PRIMARY_ERAT_HIT | Primary ERAT hit42 | 0, 1, 2, 3 | |
| PM_LSU1_REJECT | LSU1 reject . | 1 | |
| PM_LSU1_SRQ_STFWD | LS1 SRQ forwarded data to a loadLSU1 SRQ store forwarded | 0, 1, 2, 3 | |
| PM_LSU1_STORE_REJECT | ls1 store reject42 | 0, 1, 2, 3 | |
| PM_LSU1_TMA_REQ_L2 | addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42 | 0, 1, 2, 3 | |
| PM_LSU1_TM_L1_HIT | Load tm hit in L142 | 0, 1, 2, 3 | |
| PM_LSU1_TM_L1_MISS | Load tm L1 miss42 | 0, 1, 2, 3 | |
| PM_LSU2_FLUSH_LRQ | LS02Flush: LRQ42 | 0, 1, 2, 3 | |
| PM_LSU2_FLUSH_SRQ | LS2 Flush: SRQ42 | 0, 1, 2, 3 | |
| PM_LSU2_FLUSH_ULD | LS3 Flush: Unaligned Load42 | 0, 1, 2, 3 | |
| PM_LSU2_L1_CAM_CANCEL | ls2 l1 tm cam cancel42 | 0, 1, 2, 3 | |
| PM_LSU2_LARX_FIN | Larx finished in LSU pipe2. | 2 | |
| PM_LSU2_LDF | LS2 Scalar Loads42 | 0, 1, 2, 3 | |
| PM_LSU2_LDX | LS0 Vector Loads42 | 0, 1, 2, 3 | |
| PM_LSU2_LMQ_LHR_MERGE | LS0 Load Merged with another cacheline request42 | 0, 1, 2, 3 | |
| PM_LSU2_PRIMARY_ERAT_HIT | Primary ERAT hit42 | 0, 1, 2, 3 | |
| PM_LSU2_REJECT | LSU2 reject . | 2 | |
| PM_LSU2_SRQ_STFWD | LS2 SRQ forwarded data to a load42 | 0, 1, 2, 3 | |
| PM_LSU2_TMA_REQ_L2 | addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42 | 0, 1, 2, 3 | |
| PM_LSU2_TM_L1_HIT | Load tm hit in L142 | 0, 1, 2, 3 | |
| PM_LSU2_TM_L1_MISS | Load tm L1 miss42 | 0, 1, 2, 3 | |
| PM_LSU3_FLUSH_LRQ | LS3 Flush: LRQ42 | 0, 1, 2, 3 | |
| PM_LSU3_FLUSH_SRQ | LS13 Flush: SRQ42 | 0, 1, 2, 3 | |
| PM_LSU3_FLUSH_ULD | LS 14Flush: Unaligned Load42 | 0, 1, 2, 3 | |
| PM_LSU3_L1_CAM_CANCEL | ls3 l1 tm cam cancel42 | 0, 1, 2, 3 | |
| PM_LSU3_LARX_FIN | Larx finished in LSU pipe3. | 3 | |
| PM_LSU3_LDF | LS3 Scalar Loads 42 | 0, 1, 2, 3 | |
| PM_LSU3_LDX | LS1 Vector Loads42 | 0, 1, 2, 3 | |
| PM_LSU3_LMQ_LHR_MERGE | LS1 Load Merge with another cacheline request42 | 0, 1, 2, 3 | |
| PM_LSU3_PRIMARY_ERAT_HIT | Primary ERAT hit42 | 0, 1, 2, 3 | |
| PM_LSU3_REJECT | LSU3 reject . | 3 | |
| PM_LSU3_SRQ_STFWD | LS3 SRQ forwarded data to a load42 | 0, 1, 2, 3 | |
| PM_LSU3_TMA_REQ_L2 | addrs only req to L2 only on the first one,Indication that Load footprint is not expanding42 | 0, 1, 2, 3 | |
| PM_LSU3_TM_L1_HIT | Load tm hit in L142 | 0, 1, 2, 3 | |
| PM_LSU3_TM_L1_MISS | Load tm L1 miss42 | 0, 1, 2, 3 | |
| PM_LSU_ERAT_MISS_PREF | LSU | 0, 1, 2, 3 | |
| PM_LSU_FIN | LSU Finished an instruction (up to 2 per cycle). | 2 | |
| PM_LSU_FLUSH_UST | LSU | 0, 1, 2, 3 | |
| PM_LSU_FOUR_TABLEWALK_CYC | Cycles when four tablewalks pending on this thread42 | 0, 1, 2, 3 | |
| PM_LSU_FX_FIN | LSU Finished a FX operation (up to 2 per cycle. | 0 | |
| PM_LSU_L1_PREF | LSU | 0, 1, 2, 3 | |
| PM_LSU_L1_SW_PREF | LSU | 0, 1, 2, 3 | |
| PM_LSU_LDF | LSU | 0, 1, 2, 3 | |
| PM_LSU_LDX | LSU | 0, 1, 2, 3 | |
| PM_LSU_LMQ_FULL_CYC | LMQ fullCycles LMQ full, | 0, 1, 2, 3 | |
| PM_LSU_LMQ_S0_ALLOC | 0.0 | 0, 1, 2, 3 | |
| PM_LSU_LMQ_S0_VALID | Slot 0 of LMQ validLMQ slot 0 valid | 0, 1, 2, 3 | |
| PM_LSU_LMQ_SRQ_EMPTY_ALL_CYC | ALL threads lsu empty (lmq and srq empty). Issue HW016541 | 2 | |
| PM_LSU_LMQ_SRQ_EMPTY_CYC | LSU empty (lmq and srq empty). | 1 | |
| PM_LSU_LRQ_S0_ALLOC | 0.0 | 0, 1, 2, 3 | |
| PM_LSU_LRQ_S0_VALID | Slot 0 of LRQ validLRQ slot 0 valid | 0, 1, 2, 3 | |
| PM_LSU_LRQ_S43_ALLOC | 0.0 | 0, 1, 2, 3 | |
| PM_LSU_LRQ_S43_VALID | LRQ slot 43 was busy42 | 0, 1, 2, 3 | |
| PM_LSU_MRK_DERAT_MISS | DERAT Reloaded (Miss). | 2 | |
| PM_LSU_NCLD | LSU | 0, 1, 2, 3 | |
| PM_LSU_NCST | Non-cachable Stores sent to nest42 | 0, 1, 2, 3 | |
| PM_LSU_REJECT | LSU Reject (up to 4 per cycle). | 0 | |
| PM_LSU_REJECT_ERAT_MISS | LSU Reject due to ERAT (up to 4 per cycles). | 1 | |
| PM_LSU_REJECT_LHS | LSU Reject due to LHS (up to 4 per cycle). | 3 | |
| PM_LSU_REJECT_LMQ_FULL | LSU reject due to LMQ full ( 4 per cycle). | 0 | |
| PM_LSU_SET_MPRED | Line already in cache at reload time42 | 0, 1, 2, 3 | |
| PM_LSU_SRQ_EMPTY_CYC | All threads srq empty. | 3 | |
| PM_LSU_SRQ_FULL_CYC | SRQ is Full. | 0 | |
| PM_LSU_SRQ_S0_ALLOC | 0.0 | 0, 1, 2, 3 | |
| PM_LSU_SRQ_S0_VALID | Slot 0 of SRQ validSRQ slot 0 valid | 0, 1, 2, 3 | |
| PM_LSU_SRQ_S39_ALLOC | 0.0 | 0, 1, 2, 3 | |
| PM_LSU_SRQ_S39_VALID | SRQ slot 39 was busy42 | 0, 1, 2, 3 | |
| PM_LSU_SRQ_SYNC | 0.0 | 0, 1, 2, 3 | |
| PM_LSU_SRQ_SYNC_CYC | A sync is in the SRQ (edge detect to count)SRQ sync duration | 0, 1, 2, 3 | |
| PM_LSU_STORE_REJECT | LSU | 0, 1, 2, 3 | |
| PM_LSU_TWO_TABLEWALK_CYC | Cycles when two tablewalks pending on this thread42 | 0, 1, 2, 3 | |
| PM_LWSYNC | threaded version, IC Misses where we got EA dir hit but no sector valids were on. ICBI took line out | 0, 1, 2, 3 | |
| PM_LWSYNC_HELD | LWSYNC held at dispatch | 0, 1, 2, 3 | |
| PM_MEM_CO | Memory castouts from this lpar. | 3 | |
| PM_MEM_LOC_THRESH_IFU | Local Memory above threshold for IFU speculation control. | 0 | |
| PM_MEM_LOC_THRESH_LSU_HIGH | Local memory above threshold for LSU medium. | 3 | |
| PM_MEM_LOC_THRESH_LSU_MED | Local memory above theshold for data prefetch. | 0 | |
| PM_MEM_PREF | Memory prefetch for this lpar. | 1 | |
| PM_MEM_READ | Reads from Memory from this lpar (includes data/inst/xlate/l1prefetch/inst prefetch). | 0 | |
| PM_MEM_RWITM | Memory rwitm for this lpar. | 2 | |
| PM_MRK_BACK_BR_CMPL | Marked branch instruction completed with a target address less than current instruction address. | 2 | |
| PM_MRK_BRU_FIN | bru marked instr finish. | 1 | |
| PM_MRK_BR_CMPL | Branch Instruction completed. | 0 | |
| PM_MRK_CRU_FIN | IFU non-branch marked instruction finished. | 2 | |
| PM_MRK_DATA_FROM_DL2L3_MOD | The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_DL2L3_MOD_CYC | Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_DL2L3_SHR | The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load. | 2 | |
| PM_MRK_DATA_FROM_DL2L3_SHR_CYC | Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_DL4 | The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load. | 2 | |
| PM_MRK_DATA_FROM_DL4_CYC | Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_DMEM | The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_DMEM_CYC | Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_L2 | The processor's data cache was reloaded from local core's L2 due to a marked load. | 0 | |
| PM_MRK_DATA_FROM_L21_MOD | The processor's data cache was reloaded with Modified (M) data from another core's L2 on the same chip due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_L21_MOD_CYC | Duration in cycles to reload with Modified (M) data from another core's L2 on the same chip due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_L21_SHR | The processor's data cache was reloaded with Shared (S) data from another core's L2 on the same chip due to a marked load. | 2 | |
| PM_MRK_DATA_FROM_L21_SHR_CYC | Duration in cycles to reload with Shared (S) data from another core's L2 on the same chip due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_L2MISS_CYC | Duration in cycles to reload from a localtion other than the local core's L2 due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_L2_CYC | Duration in cycles to reload from local core's L2 due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST | The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load. | 2 | |
| PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC | Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER | The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC | Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_L2_MEPF | The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_L2_MEPF_CYC | Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_L2_NO_CONFLICT | The processor's data cache was reloaded from local core's L2 without conflict due to a marked load. | 0 | |
| PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC | Duration in cycles to reload from local core's L2 without conflict due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_L3 | The processor's data cache was reloaded from local core's L3 due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_L31_ECO_MOD | The processor's data cache was reloaded with Modified (M) data from another core's ECO L3 on the same chip due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_L31_ECO_MOD_CYC | Duration in cycles to reload with Modified (M) data from another core's ECO L3 on the same chip due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_L31_ECO_SHR | The processor's data cache was reloaded with Shared (S) data from another core's ECO L3 on the same chip due to a marked load. | 2 | |
| PM_MRK_DATA_FROM_L31_ECO_SHR_CYC | Duration in cycles to reload with Shared (S) data from another core's ECO L3 on the same chip due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_L31_MOD | The processor's data cache was reloaded with Modified (M) data from another core's L3 on the same chip due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_L31_MOD_CYC | Duration in cycles to reload with Modified (M) data from another core's L3 on the same chip due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_L31_SHR | The processor's data cache was reloaded with Shared (S) data from another core's L3 on the same chip due to a marked load. | 0 | |
| PM_MRK_DATA_FROM_L31_SHR_CYC | Duration in cycles to reload with Shared (S) data from another core's L3 on the same chip due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_L3MISS_CYC | Duration in cycles to reload from a localtion other than the local core's L3 due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_L3_CYC | Duration in cycles to reload from local core's L3 due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_L3_DISP_CONFLICT | The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load. | 2 | |
| PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC | Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_L3_MEPF | The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_L3_MEPF_CYC | Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_L3_NO_CONFLICT | The processor's data cache was reloaded from local core's L3 without conflict due to a marked load. | 0 | |
| PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC | Duration in cycles to reload from local core's L3 without conflict due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_LL4 | The processor's data cache was reloaded from the local chip's L4 cache due to a marked load. | 0 | |
| PM_MRK_DATA_FROM_LL4_CYC | Duration in cycles to reload from the local chip's L4 cache due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_LMEM | The processor's data cache was reloaded from the local chip's Memory due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_LMEM_CYC | Duration in cycles to reload from the local chip's Memory due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_MEMORY | The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_MEMORY_CYC | Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_OFF_CHIP_CACHE | The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC | Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_ON_CHIP_CACHE | The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load. | 0 | |
| PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC | Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_RL2L3_MOD | The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_RL2L3_MOD_CYC | Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_RL2L3_SHR | The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load. | 0 | |
| PM_MRK_DATA_FROM_RL2L3_SHR_CYC | Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_RL4 | The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load. | 1 | |
| PM_MRK_DATA_FROM_RL4_CYC | Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load. | 3 | |
| PM_MRK_DATA_FROM_RMEM | The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load. | 2 | |
| PM_MRK_DATA_FROM_RMEM_CYC | Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load. | 1 | |
| PM_MRK_DCACHE_RELOAD_INTV | Combined Intervention event. | 3 | |
| PM_MRK_DERAT_MISS_16G | Marked Data ERAT Miss (Data TLB Access) page size 16G. | 3 | |
| PM_MRK_DERAT_MISS_16M | Marked Data ERAT Miss (Data TLB Access) page size 16M. | 2 | |
| PM_MRK_DERAT_MISS_4K | Marked Data ERAT Miss (Data TLB Access) page size 4K. | 0 | |
| PM_MRK_DERAT_MISS_64K | Marked Data ERAT Miss (Data TLB Access) page size 64K. | 1 | |
| PM_MRK_DFU_FIN | Decimal Unit marked Instruction Finish. | 1 | |
| PM_MRK_DPTEG_FROM_DL2L3_MOD | A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. | 3 | |
| PM_MRK_DPTEG_FROM_DL2L3_SHR | A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. | 2 | |
| PM_MRK_DPTEG_FROM_DL4 | A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request. | 2 | |
| PM_MRK_DPTEG_FROM_DMEM | A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request. | 3 | |
| PM_MRK_DPTEG_FROM_L2 | A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request. | 0 | |
| PM_MRK_DPTEG_FROM_L21_MOD | A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L2 on the same chip due to a marked data side request. | 3 | |
| PM_MRK_DPTEG_FROM_L21_SHR | A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L2 on the same chip due to a marked data side request. | 2 | |
| PM_MRK_DPTEG_FROM_L2MISS | A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a marked data side request. | 0 | |
| PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_LDHITST | A Page Table Entry was loaded into the TLB from local core's L2 with load hit store conflict due to a marked data side request. | 2 | |
| PM_MRK_DPTEG_FROM_L2_DISP_CONFLICT_OTHER | A Page Table Entry was loaded into the TLB from local core's L2 with dispatch conflict due to a marked data side request. | 3 | |
| PM_MRK_DPTEG_FROM_L2_MEPF | A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. | 1 | |
| PM_MRK_DPTEG_FROM_L2_NO_CONFLICT | A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request. | 0 | |
| PM_MRK_DPTEG_FROM_L3 | A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. | 3 | |
| PM_MRK_DPTEG_FROM_L31_ECO_MOD | A Page Table Entry was loaded into the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data side request. | 3 | |
| PM_MRK_DPTEG_FROM_L31_ECO_SHR | A Page Table Entry was loaded into the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data side request. | 2 | |
| PM_MRK_DPTEG_FROM_L31_MOD | A Page Table Entry was loaded into the TLB with Modified (M) data from another core's L3 on the same chip due to a marked data side request. | 1 | |
| PM_MRK_DPTEG_FROM_L31_SHR | A Page Table Entry was loaded into the TLB with Shared (S) data from another core's L3 on the same chip due to a marked data side request. | 0 | |
| PM_MRK_DPTEG_FROM_L3MISS | A Page Table Entry was loaded into the TLB from a localtion other than the local core's L3 due to a marked data side request. | 3 | |
| PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT | A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. | 2 | |
| PM_MRK_DPTEG_FROM_L3_MEPF | A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request. | 1 | |
| PM_MRK_DPTEG_FROM_L3_NO_CONFLICT | A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request. | 0 | |
| PM_MRK_DPTEG_FROM_LL4 | A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request. | 0 | |
| PM_MRK_DPTEG_FROM_LMEM | A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request. | 1 | |
| PM_MRK_DPTEG_FROM_MEMORY | A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request. | 1 | |
| PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE | A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request. | 3 | |
| PM_MRK_DPTEG_FROM_ON_CHIP_CACHE | A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request. | 0 | |
| PM_MRK_DPTEG_FROM_RL2L3_MOD | A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request. | 1 | |
| PM_MRK_DPTEG_FROM_RL2L3_SHR | A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request. | 0 | |
| PM_MRK_DPTEG_FROM_RL4 | A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request. | 1 | |
| PM_MRK_DPTEG_FROM_RMEM | A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. | 2 | |
| PM_MRK_DTLB_MISS_16G | Marked Data TLB Miss page size 16G. | 0 | |
| PM_MRK_DTLB_MISS_16M | Marked Data TLB Miss page size 16M. | 3 | |
| PM_MRK_DTLB_MISS_4K | Marked Data TLB Miss page size 4k. | 1 | |
| PM_MRK_DTLB_MISS_64K | Marked Data TLB Miss page size 64K. | 2 | |
| PM_MRK_FAB_RSP_BKILL | Marked store had to do a bkill. | 3 | |
| PM_MRK_FAB_RSP_BKILL_CYC | cycles L2 RC took for a bkill. | 1 | |
| PM_MRK_FAB_RSP_CLAIM_RTY | Sampled store did a rwitm and got a rty. | 2 | |
| PM_MRK_FAB_RSP_DCLAIM | Marked store had to do a dclaim. | 2 | |
| PM_MRK_FAB_RSP_DCLAIM_CYC | cycles L2 RC took for a dclaim. | 1 | |
| PM_MRK_FAB_RSP_MATCH | ttype and cresp matched as specified in MMCR1. | 2 | |
| PM_MRK_FAB_RSP_MATCH_CYC | cresp/ttype match cycles. | 3 | |
| PM_MRK_FAB_RSP_RD_RTY | Sampled L2 reads retry count. | 3 | |
| PM_MRK_FAB_RSP_RD_T_INTV | Sampled Read got a T intervention. | 0 | |
| PM_MRK_FAB_RSP_RWITM_CYC | cycles L2 RC took for a rwitm. | 3 | |
| PM_MRK_FAB_RSP_RWITM_RTY | Sampled store did a rwitm and got a rty. | 1 | |
| PM_MRK_FILT_MATCH | Marked filter Match. | 2 | |
| PM_MRK_FIN_STALL_CYC | Marked instruction Finish Stall cycles (marked finish after NTC) (use edge detect to count #). | 0 | |
| PM_MRK_FXU_FIN | fxu marked instr finish. | 1 | |
| PM_MRK_GRP_CMPL | marked instruction finished (completed). | 3 | |
| PM_MRK_GRP_IC_MISS | Marked Group experienced I cache miss. | 3 | |
| PM_MRK_GRP_NTC | Marked group ntc cycles. | 2 | |
| PM_MRK_INST_DECODED | marked instruction decoded. Name from ISU? | 1 | |
| PM_MRK_INST_FIN | marked instr finish any unit . | 2 | |
| PM_MRK_INST_ISSUED | Marked instruction issued. | 0 | |
| PM_MRK_INST_TIMEO | marked Instruction finish timeout (instruction lost). | 3 | |
| PM_MRK_L2_RC_DISP | Marked Instruction RC dispatched in L2. | 1 | |
| PM_MRK_L2_RC_DONE | Marked RC done. | 2 | |
| PM_MRK_LARX_FIN | Larx finished . | 3 | |
| PM_MRK_LD_MISS_EXPOSED | Marked Load exposed Miss (use edge detect to count #) | 0 | |
| PM_MRK_LD_MISS_EXPOSED_CYC | Marked Load exposed Miss (use edge detect to count #). | 0 | |
| PM_MRK_LD_MISS_L1_CYC | Marked ld latency. | 3 | |
| PM_MRK_LSU_FIN | lsu marked instr finish. | 3 | |
| PM_MRK_LSU_FLUSH | Flush: (marked) : All Cases42 | 0, 1, 2, 3 | |
| PM_MRK_LSU_FLUSH_LRQ | Flush: (marked) LRQMarked LRQ flushes | 0, 1, 2, 3 | |
| PM_MRK_LSU_FLUSH_SRQ | Flush: (marked) SRQMarked SRQ lhs flushes | 0, 1, 2, 3 | |
| PM_MRK_LSU_FLUSH_ULD | Flush: (marked) Unaligned LoadMarked unaligned load flushes | 0, 1, 2, 3 | |
| PM_MRK_LSU_FLUSH_UST | Flush: (marked) Unaligned StoreMarked unaligned store flushes | 0, 1, 2, 3 | |
| PM_MRK_LSU_REJECT | LSU marked reject (up to 2 per cycle). | 3 | |
| PM_MRK_LSU_REJECT_ERAT_MISS | LSU marked reject due to ERAT (up to 2 per cycle). | 2 | |
| PM_MRK_NTF_FIN | Marked next to finish instruction finished. | 1 | |
| PM_MRK_RUN_CYC | Marked run cycles. | 0 | |
| PM_MRK_SRC_PREF_TRACK_EFF | Marked src pref track was effective. | 0 | |
| PM_MRK_SRC_PREF_TRACK_INEFF | Prefetch tracked was ineffective for marked src. | 2 | |
| PM_MRK_SRC_PREF_TRACK_MOD | Prefetch tracked was moderate for marked src. | 3 | |
| PM_MRK_SRC_PREF_TRACK_MOD_L2 | Marked src Prefetch Tracked was moderate (source L2). | 0 | |
| PM_MRK_SRC_PREF_TRACK_MOD_L3 | Prefetch tracked was moderate (L3 hit) for marked src. | 2 | |
| PM_MRK_STALL_CMPLU_CYC | Marked Group Completion Stall cycles (use edge detect to count #). | 2 | |
| PM_MRK_STCX_FAIL | marked stcx failed. | 2 | |
| PM_MRK_ST_CMPL_INT | marked store complete (data home) with intervention. | 2 | |
| PM_MRK_ST_DRAIN_TO_L2DISP_CYC | cycles to drain st from core to L2. | 2 | |
| PM_MRK_ST_FWD | Marked st forwards. | 2 | |
| PM_MRK_ST_L2DISP_TO_CMPL_CYC | cycles from L2 rc disp to l2 rc completion. | 0 | |
| PM_MRK_ST_NEST | Marked store sent to nest. | 1 | |
| PM_MRK_TGT_PREF_TRACK_EFF | Marked target pref track was effective. | 0 | |
| PM_MRK_TGT_PREF_TRACK_INEFF | Prefetch tracked was ineffective for marked target. | 2 | |
| PM_MRK_TGT_PREF_TRACK_MOD | Prefetch tracked was moderate for marked target. | 3 | |
| PM_MRK_TGT_PREF_TRACK_MOD_L2 | Marked target Prefetch Tracked was moderate (source L2). | 0 | |
| PM_MRK_TGT_PREF_TRACK_MOD_L3 | Prefetch tracked was moderate (L3 hit) for marked target. | 2 | |
| PM_MRK_VSU_FIN | vsu (fpu) marked instr finish. | 2 | |
| PM_MULT_MRK | mult marked instr. | 2 | |
| PM_NESTED_TEND | Completion time nested tend | 0, 1, 2, 3 | |
| PM_NEST_REF_CLK | Nest reference clocks. | 2 | |
| PM_NON_FAV_TBEGIN | Dispatch time non favored tbegin | 0, 1, 2, 3 | |
| PM_NTCG_ALL_FIN | Ccycles after all instructions have finished to group completed. | 1 | |
| PM_OUTER_TBEGIN | Completion time outer tbegin | 0, 1, 2, 3 | |
| PM_OUTER_TEND | Completion time outer tend | 0, 1, 2, 3 | |
| PM_PMC1_OVERFLOW | Overflow from counter 1. | 1 | |
| PM_PMC2_OVERFLOW | Overflow from counter 2. | 2 | |
| PM_PMC2_REWIND | PMC2 Rewind Event (did not match condition). | 2 | |
| PM_PMC2_SAVED | PMC2 Rewind Value saved (matched condition). | 0 | |
| PM_PMC3_OVERFLOW | Overflow from counter 3. | 3 | |
| PM_PMC4_OVERFLOW | Overflow from counter 4. | 0 | |
| PM_PMC4_REWIND | PMC4 Rewind Event (did not match condition). | 0 | |
| PM_PMC4_SAVED | PMC4 Rewind Value saved (matched condition). | 2 | |
| PM_PMC5_OVERFLOW | Overflow from counter 5. | 0 | |
| PM_PMC6_OVERFLOW | Overflow from counter 6. | 2 | |
| PM_PREF_TRACKED | Total number of Prefetch Operations that were tracked. | 1 | |
| PM_PREF_TRACK_EFF | Prefetch Tracked was effective. | 0 | |
| PM_PREF_TRACK_INEFF | Prefetch tracked was ineffective. | 2 | |
| PM_PREF_TRACK_MOD | Prefetch tracked was moderate. | 3 | |
| PM_PREF_TRACK_MOD_L2 | Prefetch Tracked was moderate (source L2). | 0 | |
| PM_PREF_TRACK_MOD_L3 | Prefetch tracked was moderate (L3). | 2 | |
| PM_PROBE_NOP_DISP | ProbeNops dispatched. | 3 | |
| PM_PTE_PREFETCH | PTE prefetches42 | 0, 1, 2, 3 | |
| PM_PUMP_CPRED | Pump prediction correct. Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate). | 0 | |
| PM_PUMP_MPRED | Pump Mis prediction Counts across all types of pumpsfor all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate). | 3 | |
| PM_RC0_ALLOC | 0.0 | 0 | |
| PM_RC0_BUSY | RC mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point) | 0 | |
| PM_RC_LIFETIME_EXC_1024 | Reload latency exceeded 1024 cyc | 2 |
0xde: Thresholdable start/stop for rc machine for sampled instruction
|
| PM_RC_LIFETIME_EXC_2048 | Threshold counter exceeded a value of 2048 | 3 |
0xde: Thresholdable start/stop for rc machine for sampled instruction
|
| PM_RC_LIFETIME_EXC_256 | Threshold counter exceed a count of 256 | 0 |
0xde: Thresholdable start/stop for rc machine for sampled instruction
|
| PM_RC_LIFETIME_EXC_32 | Reload latency exceeded 32 cyc | 1 |
0xde: Thresholdable start/stop for rc machine for sampled instruction
|
| PM_RC_USAGE | Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 RC machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running | 2 | |
| PM_REAL_SRQ_FULL | Out of real srq entries. | 1 | |
| PM_RUN_CYC_SMT2_MODE | Cycles run latch is set and core is in SMT2 mode. | 2 | |
| PM_RUN_CYC_SMT2_SHRD_MODE | Cycles run latch is set and core is in SMT2-shared mode. | 1 | |
| PM_RUN_CYC_SMT2_SPLIT_MODE | Cycles run latch is set and core is in SMT2-split mode. | 0 | |
| PM_RUN_CYC_SMT4_MODE | Cycles run latch is set and core is in SMT4 mode. | 1 | |
| PM_RUN_CYC_SMT8_MODE | Cycles run latch is set and core is in SMT8 mode. | 3 | |
| PM_RUN_CYC_ST_MODE | Cycles run latch is set and core is in ST mode. | 0 | |
| PM_RUN_SPURR | Run SPURR. | 0 | |
| PM_SEC_ERAT_HIT | secondary ERAT Hit42 | 0, 1, 2, 3 | |
| PM_SHL_CREATED | Store-Hit-Load Table Entry Created | 0, 1, 2, 3 | |
| PM_SHL_ST_CONVERT | Store-Hit-Load Table Read Hit with entry Enabled | 0, 1, 2, 3 | |
| PM_SHL_ST_DISABLE | Store-Hit-Load Table Read Hit with entry Disabled (entry was disabled due to the entry shown to not prevent the flush) | 0, 1, 2, 3 | |
| PM_SN0_ALLOC | 0.0 | 1 | |
| PM_SN0_BUSY | SN mach 0 Busy. Used by PMU to sample ave RC livetime(mach0 used as sample point) | 1 | |
| PM_SNOOP_TLBIE | TLBIE snoopSnoop TLBIE | 0, 1, 2, 3 | |
| PM_SN_USAGE | Continuous 16 cycle(2to1) window where this signals rotates thru sampling each L2 SN machine busy. PMU uses this wave to then do 16 cyc count to sample total number of machs running | 3 | |
| PM_STALL_END_GCT_EMPTY | Count ended because GCT went empty. | 0 | |
| PM_STCX_FAIL | stcx failed . | 0 | |
| PM_STCX_LSU | STCX executed reported at sent to nest42 | 0, 1, 2, 3 | |
| PM_ST_CMPL | Store completion count. | 1 | |
| PM_ST_FWD | Store forwards that finished. | 1 | |
| PM_SUSPENDED | Counter OFF. | 0, 1, 2, 3 | |
| PM_SWAP_CANCEL | SWAP cancel , rtag not available | 0, 1, 2, 3 | |
| PM_SWAP_CANCEL_GPR | SWAP cancel , rtag not available for gpr | 0, 1, 2, 3 | |
| PM_SWAP_COMPLETE | swap cast in completed | 0, 1, 2, 3 | |
| PM_SWAP_COMPLETE_GPR | swap cast in completed fpr gpr | 0, 1, 2, 3 | |
| PM_SYNC_MRK_BR_LINK | Marked Branch and link branch that can cause a synchronous interrupt. | 0 | |
| PM_SYNC_MRK_BR_MPRED | Marked Branch mispredict that can cause a synchronous interrupt. | 0 | |
| PM_SYNC_MRK_FX_DIVIDE | Marked fixed point divide that can cause a synchronous interrupt. | 0 | |
| PM_SYNC_MRK_L2HIT | Marked L2 Hits that can throw a synchronous interrupt. | 0 | |
| PM_SYNC_MRK_L2MISS | Marked L2 Miss that can throw a synchronous interrupt. | 0 | |
| PM_SYNC_MRK_L3MISS | Marked L3 misses that can throw a synchronous interrupt. | 0 | |
| PM_SYNC_MRK_PROBE_NOP | Marked probeNops which can cause synchronous interrupts. | 0 | |
| PM_SYS_PUMP_CPRED | Initial and Final Pump Scope and data sourced across this scope was system pump for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate). | 2 | |
| PM_SYS_PUMP_MPRED | Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope(Chip/Group) OR Final Pump Scope(system) got data from source that was at smaller scope(Chip/group) Final pump was system pump and initial pump was chip or group or | 2 | |
| PM_SYS_PUMP_MPRED_RTY | Final Pump Scope(system) to get data sourced, ended up larger than Initial Pump Scope (Chip or Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate). | 3 | |
| PM_TABLEWALK_CYC | Tablewalk Active. | 0 | |
| PM_TABLEWALK_CYC_PREF | tablewalk qualified for pte prefetches42 | 0, 1, 2, 3 | |
| PM_TABORT_TRECLAIM | Completion time tabortnoncd, tabortcd, treclaim | 0, 1, 2, 3 | |
| PM_TEND_PEND_CYC | TEND latency per thread42 | 0, 1, 2, 3 | |
| PM_THRD_ALL_RUN_CYC | All Threads in Run_cycles (was both threads in run_cycles). | 1 | |
| PM_THRD_GRP_CMPL_BOTH_CYC | Two threads finished same cycle (gated by run latch). | 0 | |
| PM_THRD_PRIO_0_1_CYC | Cycles thread running at priority level 0 or 1 | 0, 1, 2, 3 | |
| PM_THRD_PRIO_2_3_CYC | Cycles thread running at priority level 2 or 3 | 0, 1, 2, 3 | |
| PM_THRD_PRIO_4_5_CYC | Cycles thread running at priority level 4 or 5 | 0, 1, 2, 3 | |
| PM_THRD_PRIO_6_7_CYC | Cycles thread running at priority level 6 or 7 | 0, 1, 2, 3 | |
| PM_THRD_REBAL_CYC | cycles rebalance was active | 0, 1, 2, 3 | |
| PM_THRESH_NOT_MET | Threshold counter did not meet threshold. | 3 | |
| PM_TLBIE_FIN | tlbie finished. | 2 | |
| PM_TLB_MISS | TLB Miss (I + D). | 1 | |
| PM_TM_BEGIN_ALL | Tm any tbegin | 0, 1, 2, 3 | |
| PM_TM_END_ALL | Tm any tend | 0, 1, 2, 3 | |
| PM_TM_FAIL_CONF_NON_TM | TEXAS fail reason @ completion | 0, 1, 2, 3 | |
| PM_TM_FAIL_CON_TM | TEXAS fail reason @ completion | 0, 1, 2, 3 | |
| PM_TM_FAIL_DISALLOW | TM fail disallow42 | 0, 1, 2, 3 | |
| PM_TM_FAIL_FOOTPRINT_OVERFLOW | TEXAS fail reason @ completion | 0, 1, 2, 3 | |
| PM_TM_FAIL_NON_TX_CONFLICT | Non transactional conflict from LSU whtver gets repoted to texas42 | 0, 1, 2, 3 | |
| PM_TM_FAIL_SELF | TEXAS fail reason @ completion | 0, 1, 2, 3 | |
| PM_TM_FAIL_TLBIE | TLBIE hit bloom filter42 | 0, 1, 2, 3 | |
| PM_TM_FAIL_TX_CONFLICT | Transactional conflict from LSU, whatever gets reported to texas 42 | 0, 1, 2, 3 | |
| PM_TM_TBEGIN | Tm nested tbegin | 0, 1, 2, 3 | |
| PM_TM_TRANS_RUN_CYC | run cycles in transactional state. | 0 | |
| PM_TM_TRANS_RUN_INST | Instructions completed in transactional state. | 2 | |
| PM_TM_TRESUME | Tm resume | 0, 1, 2, 3 | |
| PM_TM_TSUSPEND | Tm suspend | 0, 1, 2, 3 | |
| PM_TM_TX_PASS_RUN_CYC | run cycles spent in successful transactions. | 1 | |
| PM_TM_TX_PASS_RUN_INST | run instructions spent in successful transactions. | 3 | |
| PM_UP_PREF_L3 | Micropartition prefetch42 | 0, 1, 2, 3 | |
| PM_UP_PREF_POINTER | Micrpartition pointer prefetches42 | 0, 1, 2, 3 | |
| PM_VSU0_16FLOP | Sixteen flops operation (SP vector versions of fdiv,fsqrt) | 0, 1, 2, 3 | |
| PM_VSU0_1FLOP | one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finishedDecode into 1,2,4 FLOP according to instr IOP, multiplied by #vector elements according to route( eg x1, x2, x4) Only if instr sends finish to ISU | 0, 1, 2, 3 | |
| PM_VSU0_2FLOP | two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) | 0, 1, 2, 3 | |
| PM_VSU0_4FLOP | four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) | 0, 1, 2, 3 | |
| PM_VSU0_8FLOP | eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) | 0, 1, 2, 3 | |
| PM_VSU0_COMPLEX_ISSUED | Complex VMX instruction issued | 0, 1, 2, 3 | |
| PM_VSU0_CY_ISSUED | Cryptographic instruction RFC02196 Issued | 0, 1, 2, 3 | |
| PM_VSU0_DD_ISSUED | 64BIT Decimal Issued | 0, 1, 2, 3 | |
| PM_VSU0_DP_2FLOP | DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg | 0, 1, 2, 3 | |
| PM_VSU0_DP_FMA | DP vector version of fmadd,fnmadd,fmsub,fnmsub | 0, 1, 2, 3 | |
| PM_VSU0_DP_FSQRT_FDIV | DP vector versions of fdiv,fsqrt | 0, 1, 2, 3 | |
| PM_VSU0_DQ_ISSUED | 128BIT Decimal Issued | 0, 1, 2, 3 | |
| PM_VSU0_EX_ISSUED | Direct move 32/64b VRFtoGPR RFC02206 Issued | 0, 1, 2, 3 | |
| PM_VSU0_FIN | VSU0 Finished an instruction | 0, 1, 2, 3 | |
| PM_VSU0_FMA | two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! | 0, 1, 2, 3 | |
| PM_VSU0_FPSCR | Move to/from FPSCR type instruction issued on Pipe 0 | 0, 1, 2, 3 | |
| PM_VSU0_FSQRT_FDIV | four flops operation (fdiv,fsqrt) Scalar Instructions only! | 0, 1, 2, 3 | |
| PM_VSU0_PERMUTE_ISSUED | Permute VMX Instruction Issued | 0, 1, 2, 3 | |
| PM_VSU0_SCALAR_DP_ISSUED | Double Precision scalar instruction issued on Pipe0 | 0, 1, 2, 3 | |
| PM_VSU0_SIMPLE_ISSUED | Simple VMX instruction issued | 0, 1, 2, 3 | |
| PM_VSU0_SINGLE | FPU single precision | 0, 1, 2, 3 | |
| PM_VSU0_SQ | Store Vector Issued | 0, 1, 2, 3 | |
| PM_VSU0_STF | FPU store (SP or DP) issued on Pipe0 | 0, 1, 2, 3 | |
| PM_VSU0_VECTOR_DP_ISSUED | Double Precision vector instruction issued on Pipe0 | 0, 1, 2, 3 | |
| PM_VSU0_VECTOR_SP_ISSUED | Single Precision vector instruction issued (executed) | 0, 1, 2, 3 | |
| PM_VSU1_16FLOP | Sixteen flops operation (SP vector versions of fdiv,fsqrt) | 0, 1, 2, 3 | |
| PM_VSU1_1FLOP | one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation finished | 0, 1, 2, 3 | |
| PM_VSU1_2FLOP | two flops operation (scalar fmadd, fnmadd, fmsub, fnmsub and DP vector versions of single flop instructions) | 0, 1, 2, 3 | |
| PM_VSU1_4FLOP | four flops operation (scalar fdiv, fsqrt, DP vector version of fmadd, fnmadd, fmsub, fnmsub, SP vector versions of single flop instructions) | 0, 1, 2, 3 | |
| PM_VSU1_8FLOP | eight flops operation (DP vector versions of fdiv,fsqrt and SP vector versions of fmadd,fnmadd,fmsub,fnmsub) | 0, 1, 2, 3 | |
| PM_VSU1_COMPLEX_ISSUED | Complex VMX instruction issued | 0, 1, 2, 3 | |
| PM_VSU1_CY_ISSUED | Cryptographic instruction RFC02196 Issued | 0, 1, 2, 3 | |
| PM_VSU1_DD_ISSUED | 64BIT Decimal Issued | 0, 1, 2, 3 | |
| PM_VSU1_DP_2FLOP | DP vector version of fmul, fsub, fcmp, fsel, fabs, fnabs, fres ,fsqrte, fneg | 0, 1, 2, 3 | |
| PM_VSU1_DP_FMA | DP vector version of fmadd,fnmadd,fmsub,fnmsub | 0, 1, 2, 3 | |
| PM_VSU1_DP_FSQRT_FDIV | DP vector versions of fdiv,fsqrt | 0, 1, 2, 3 | |
| PM_VSU1_DQ_ISSUED | 128BIT Decimal Issued | 0, 1, 2, 3 | |
| PM_VSU1_EX_ISSUED | Direct move 32/64b VRFtoGPR RFC02206 Issued | 0, 1, 2, 3 | |
| PM_VSU1_FIN | VSU1 Finished an instruction | 0, 1, 2, 3 | |
| PM_VSU1_FMA | two flops operation (fmadd, fnmadd, fmsub, fnmsub) Scalar instructions only! | 0, 1, 2, 3 | |
| PM_VSU1_FPSCR | Move to/from FPSCR type instruction issued on Pipe 0 | 0, 1, 2, 3 | |
| PM_VSU1_FSQRT_FDIV | four flops operation (fdiv,fsqrt) Scalar Instructions only! | 0, 1, 2, 3 | |
| PM_VSU1_PERMUTE_ISSUED | Permute VMX Instruction Issued | 0, 1, 2, 3 | |
| PM_VSU1_SCALAR_DP_ISSUED | Double Precision scalar instruction issued on Pipe1 | 0, 1, 2, 3 | |
| PM_VSU1_SIMPLE_ISSUED | Simple VMX instruction issued | 0, 1, 2, 3 | |
| PM_VSU1_SINGLE | FPU single precision | 0, 1, 2, 3 | |
| PM_VSU1_SQ | Store Vector Issued | 0, 1, 2, 3 | |
| PM_VSU1_STF | FPU store (SP or DP) issued on Pipe1 | 0, 1, 2, 3 | |
| PM_VSU1_VECTOR_DP_ISSUED | Double Precision vector instruction issued on Pipe1 | 0, 1, 2, 3 | |
| PM_VSU1_VECTOR_SP_ISSUED | Single Precision vector instruction issued (executed) | 0, 1, 2, 3 |
Speed, it seems to me, provides the one genuinely modern pleasure.- Aldous Huxley