This is a list of all ppc64 POWER5's performance counter event types.
| Name | Description | Counters usable | Group |
| CYCLES | Processor Cycles using continuous sampling | 3 | |
| PM_RUN_CYC_GRP1 | Run cycles | 0 | Group 1 pm_utilization |
| PM_IOPS_CMPL_GRP1 | IOPS instructions completed | 1 | Group 1 pm_utilization |
| PM_INST_DISP_GRP1 | Instructions dispatched | 2 | Group 1 pm_utilization |
| PM_CYC_GRP1 | Processor cycles | 3 | Group 1 pm_utilization |
| PM_INST_CMPL_GRP1 | Instructions completed | 4 | Group 1 pm_utilization |
| PM_RUN_CYC_GRP1 | Run cycles | 5 | Group 1 pm_utilization |
| PM_1PLUS_PPC_CMPL_GRP2 | One or more PPC instruction completed | 0 | Group 2 pm_completion |
| PM_GCT_EMPTY_CYC_GRP2 | Cycles GCT empty | 1 | Group 2 pm_completion |
| PM_GRP_CMPL_GRP2 | Group completed | 2 | Group 2 pm_completion |
| PM_CYC_GRP2 | Processor cycles | 3 | Group 2 pm_completion |
| PM_INST_CMPL_GRP2 | Instructions completed | 4 | Group 2 pm_completion |
| PM_RUN_CYC_GRP2 | Run cycles | 5 | Group 2 pm_completion |
| PM_GRP_DISP_VALID_GRP3 | Group dispatch valid | 0 | Group 3 pm_group_dispatch |
| PM_GRP_DISP_REJECT_GRP3 | Group dispatch rejected | 1 | Group 3 pm_group_dispatch |
| PM_GRP_DISP_BLK_SB_CYC_GRP3 | Cycles group dispatch blocked by scoreboard | 2 | Group 3 pm_group_dispatch |
| PM_INST_DISP_GRP3 | Instructions dispatched | 3 | Group 3 pm_group_dispatch |
| PM_INST_CMPL_GRP3 | Instructions completed | 4 | Group 3 pm_group_dispatch |
| PM_RUN_CYC_GRP3 | Run cycles | 5 | Group 3 pm_group_dispatch |
| PM_0INST_CLB_CYC_GRP4 | Cycles no instructions in CLB | 0 | Group 4 pm_clb1 |
| PM_2INST_CLB_CYC_GRP4 | Cycles 2 instructions in CLB | 1 | Group 4 pm_clb1 |
| PM_CLB_EMPTY_CYC_GRP4 | Cycles CLB empty | 2 | Group 4 pm_clb1 |
| PM_MRK_DATA_FROM_L35_MOD_CYC_GRP4 | Marked load latency from L3.5 modified | 3 | Group 4 pm_clb1 |
| PM_INST_CMPL_GRP4 | Instructions completed | 4 | Group 4 pm_clb1 |
| PM_RUN_CYC_GRP4 | Run cycles | 5 | Group 4 pm_clb1 |
| PM_5INST_CLB_CYC_GRP5 | Cycles 5 instructions in CLB | 0 | Group 5 pm_clb2 |
| PM_6INST_CLB_CYC_GRP5 | Cycles 6 instructions in CLB | 1 | Group 5 pm_clb2 |
| PM_MRK_LSU_SRQ_INST_VALID_GRP5 | Marked instruction valid in SRQ | 2 | Group 5 pm_clb2 |
| PM_IOPS_CMPL_GRP5 | IOPS instructions completed | 3 | Group 5 pm_clb2 |
| PM_INST_CMPL_GRP5 | Instructions completed | 4 | Group 5 pm_clb2 |
| PM_RUN_CYC_GRP5 | Run cycles | 5 | Group 5 pm_clb2 |
| PM_GCT_NOSLOT_CYC_GRP6 | Cycles no GCT slot allocated | 0 | Group 6 pm_gct_empty |
| PM_GCT_NOSLOT_IC_MISS_GRP6 | No slot in GCT caused by I cache miss | 1 | Group 6 pm_gct_empty |
| PM_GCT_NOSLOT_SRQ_FULL_GRP6 | No slot in GCT caused by SRQ full | 2 | Group 6 pm_gct_empty |
| PM_GCT_NOSLOT_BR_MPRED_GRP6 | No slot in GCT caused by branch mispredict | 3 | Group 6 pm_gct_empty |
| PM_INST_CMPL_GRP6 | Instructions completed | 4 | Group 6 pm_gct_empty |
| PM_RUN_CYC_GRP6 | Run cycles | 5 | Group 6 pm_gct_empty |
| PM_GCT_USAGE_00to59_CYC_GRP7 | Cycles GCT less than 60% full | 0 | Group 7 pm_gct_usage |
| PM_GCT_USAGE_60to79_CYC_GRP7 | Cycles GCT 60-79% full | 1 | Group 7 pm_gct_usage |
| PM_GCT_USAGE_80to99_CYC_GRP7 | Cycles GCT 80-99% full | 2 | Group 7 pm_gct_usage |
| PM_GCT_FULL_CYC_GRP7 | Cycles GCT full | 3 | Group 7 pm_gct_usage |
| PM_INST_CMPL_GRP7 | Instructions completed | 4 | Group 7 pm_gct_usage |
| PM_RUN_CYC_GRP7 | Run cycles | 5 | Group 7 pm_gct_usage |
| PM_LSU_LRQ_S0_ALLOC_GRP8 | LRQ slot 0 allocated | 0 | Group 8 pm_lsu1 |
| PM_LSU_LRQ_S0_VALID_GRP8 | LRQ slot 0 valid | 1 | Group 8 pm_lsu1 |
| PM_LSU_LMQ_S0_ALLOC_GRP8 | LMQ slot 0 allocated | 2 | Group 8 pm_lsu1 |
| PM_LSU_LMQ_S0_VALID_GRP8 | LMQ slot 0 valid | 3 | Group 8 pm_lsu1 |
| PM_INST_CMPL_GRP8 | Instructions completed | 4 | Group 8 pm_lsu1 |
| PM_RUN_CYC_GRP8 | Run cycles | 5 | Group 8 pm_lsu1 |
| PM_LSU_SRQ_S0_ALLOC_GRP9 | SRQ slot 0 allocated | 0 | Group 9 pm_lsu2 |
| PM_LSU_SRQ_S0_VALID_GRP9 | SRQ slot 0 valid | 1 | Group 9 pm_lsu2 |
| PM_LSU_SRQ_SYNC_CYC_GRP9 | SRQ sync duration | 2 | Group 9 pm_lsu2 |
| PM_LSU_SRQ_FULL_CYC_GRP9 | Cycles SRQ full | 3 | Group 9 pm_lsu2 |
| PM_INST_CMPL_GRP9 | Instructions completed | 4 | Group 9 pm_lsu2 |
| PM_RUN_CYC_GRP9 | Run cycles | 5 | Group 9 pm_lsu2 |
| PM_LSU_SRQ_STFWD_GRP10 | SRQ store forwarded | 0 | Group 10 pm_lsu3 |
| PM_LSU_LMQ_SRQ_EMPTY_CYC_GRP10 | Cycles LMQ and SRQ empty | 1 | Group 10 pm_lsu3 |
| PM_LSU_LMQ_LHR_MERGE_GRP10 | LMQ LHR merges | 2 | Group 10 pm_lsu3 |
| PM_LSU_SRQ_EMPTY_CYC_GRP10 | Cycles SRQ empty | 3 | Group 10 pm_lsu3 |
| PM_INST_CMPL_GRP10 | Instructions completed | 4 | Group 10 pm_lsu3 |
| PM_RUN_CYC_GRP10 | Run cycles | 5 | Group 10 pm_lsu3 |
| PM_INST_FROM_L2MISS_GRP11 | Instructions fetched missed L2 | 0 | Group 11 pm_prefetch1 |
| PM_INST_FETCH_CYC_GRP11 | Cycles at least 1 instruction fetched | 1 | Group 11 pm_prefetch1 |
| PM_DC_PREF_STREAM_ALLOC_BLK_GRP11 | D cache out of prefech streams | 2 | Group 11 pm_prefetch1 |
| PM_DC_PREF_STREAM_ALLOC_GRP11 | D cache new prefetch stream allocated | 3 | Group 11 pm_prefetch1 |
| PM_INST_CMPL_GRP11 | Instructions completed | 4 | Group 11 pm_prefetch1 |
| PM_RUN_CYC_GRP11 | Run cycles | 5 | Group 11 pm_prefetch1 |
| PM_IOPS_CMPL_GRP12 | IOPS instructions completed | 0 | Group 12 pm_prefetch2 |
| PM_CLB_FULL_CYC_GRP12 | Cycles CLB full | 1 | Group 12 pm_prefetch2 |
| PM_L1_PREF_GRP12 | L1 cache data prefetches | 2 | Group 12 pm_prefetch2 |
| PM_IC_PREF_INSTALL_GRP12 | Instruction prefetched installed in prefetch | 3 | Group 12 pm_prefetch2 |
| PM_INST_CMPL_GRP12 | Instructions completed | 4 | Group 12 pm_prefetch2 |
| PM_RUN_CYC_GRP12 | Run cycles | 5 | Group 12 pm_prefetch2 |
| PM_LSU_BUSY_REJECT_GRP13 | LSU busy due to reject | 0 | Group 13 pm_prefetch3 |
| PM_1INST_CLB_CYC_GRP13 | Cycles 1 instruction in CLB | 1 | Group 13 pm_prefetch3 |
| PM_L2_PREF_GRP13 | L2 cache prefetches | 2 | Group 13 pm_prefetch3 |
| PM_IOPS_CMPL_GRP13 | IOPS instructions completed | 3 | Group 13 pm_prefetch3 |
| PM_INST_CMPL_GRP13 | Instructions completed | 4 | Group 13 pm_prefetch3 |
| PM_RUN_CYC_GRP13 | Run cycles | 5 | Group 13 pm_prefetch3 |
| PM_LSU0_REJECT_SRQ_LHS_GRP14 | LSU0 SRQ rejects | 0 | Group 14 pm_prefetch4 |
| PM_LSU1_REJECT_SRQ_LHS_GRP14 | LSU1 SRQ rejects | 1 | Group 14 pm_prefetch4 |
| PM_DC_PREF_DST_GRP14 | DST (Data Stream Touch) stream start | 2 | Group 14 pm_prefetch4 |
| PM_L2_PREF_GRP14 | L2 cache prefetches | 3 | Group 14 pm_prefetch4 |
| PM_INST_CMPL_GRP14 | Instructions completed | 4 | Group 14 pm_prefetch4 |
| PM_RUN_CYC_GRP14 | Run cycles | 5 | Group 14 pm_prefetch4 |
| PM_LSU_REJECT_ERAT_MISS_GRP15 | LSU reject due to ERAT miss | 0 | Group 15 pm_lsu_reject1 |
| PM_LSU_REJECT_LMQ_FULL_GRP15 | LSU reject due to LMQ full or missed data coming | 1 | Group 15 pm_lsu_reject1 |
| PM_FLUSH_IMBAL_GRP15 | Flush caused by thread GCT imbalance | 2 | Group 15 pm_lsu_reject1 |
| PM_MRK_LSU_FLUSH_SRQ_GRP15 | Marked SRQ flushes | 3 | Group 15 pm_lsu_reject1 |
| PM_INST_CMPL_GRP15 | Instructions completed | 4 | Group 15 pm_lsu_reject1 |
| PM_RUN_CYC_GRP15 | Run cycles | 5 | Group 15 pm_lsu_reject1 |
| PM_LSU0_REJECT_RELOAD_CDF_GRP16 | LSU0 reject due to reload CDF or tag update collision | 0 | Group 16 pm_lsu_reject2 |
| PM_LSU1_REJECT_RELOAD_CDF_GRP16 | LSU1 reject due to reload CDF or tag update collision | 1 | Group 16 pm_lsu_reject2 |
| PM_IOPS_CMPL_GRP16 | IOPS instructions completed | 2 | Group 16 pm_lsu_reject2 |
| PM_L1_WRITE_CYC_GRP16 | Cycles writing to instruction L1 | 3 | Group 16 pm_lsu_reject2 |
| PM_INST_CMPL_GRP16 | Instructions completed | 4 | Group 16 pm_lsu_reject2 |
| PM_RUN_CYC_GRP16 | Run cycles | 5 | Group 16 pm_lsu_reject2 |
| PM_LSU0_REJECT_ERAT_MISS_GRP17 | LSU0 reject due to ERAT miss | 0 | Group 17 pm_lsu_reject3 |
| PM_LSU1_REJECT_ERAT_MISS_GRP17 | LSU1 reject due to ERAT miss | 1 | Group 17 pm_lsu_reject3 |
| PM_LWSYNC_HELD_GRP17 | LWSYNC held at dispatch | 2 | Group 17 pm_lsu_reject3 |
| PM_TLBIE_HELD_GRP17 | TLBIE held at dispatch | 3 | Group 17 pm_lsu_reject3 |
| PM_INST_CMPL_GRP17 | Instructions completed | 4 | Group 17 pm_lsu_reject3 |
| PM_RUN_CYC_GRP17 | Run cycles | 5 | Group 17 pm_lsu_reject3 |
| PM_LSU0_REJECT_LMQ_FULL_GRP18 | LSU0 reject due to LMQ full or missed data coming | 0 | Group 18 pm_lsu_reject4 |
| PM_LSU1_REJECT_LMQ_FULL_GRP18 | LSU1 reject due to LMQ full or missed data coming | 1 | Group 18 pm_lsu_reject4 |
| PM_IOPS_CMPL_GRP18 | IOPS instructions completed | 2 | Group 18 pm_lsu_reject4 |
| PM_BR_ISSUED_GRP18 | Branches issued | 3 | Group 18 pm_lsu_reject4 |
| PM_INST_CMPL_GRP18 | Instructions completed | 4 | Group 18 pm_lsu_reject4 |
| PM_RUN_CYC_GRP18 | Run cycles | 5 | Group 18 pm_lsu_reject4 |
| PM_LSU_REJECT_SRQ_LHS_GRP19 | LSU SRQ rejects | 0 | Group 19 pm_lsu_reject5 |
| PM_LSU_REJECT_RELOAD_CDF_GRP19 | LSU reject due to reload CDF or tag update collision | 1 | Group 19 pm_lsu_reject5 |
| PM_LSU_FLUSH_GRP19 | Flush initiated by LSU | 2 | Group 19 pm_lsu_reject5 |
| PM_FLUSH_GRP19 | Flushes | 3 | Group 19 pm_lsu_reject5 |
| PM_INST_CMPL_GRP19 | Instructions completed | 4 | Group 19 pm_lsu_reject5 |
| PM_RUN_CYC_GRP19 | Run cycles | 5 | Group 19 pm_lsu_reject5 |
| PM_IOPS_CMPL_GRP20 | IOPS instructions completed | 0 | Group 20 pm_flush1 |
| PM_LSU_FLUSH_UST_GRP20 | SRQ unaligned store flushes | 1 | Group 20 pm_flush1 |
| PM_FLUSH_IMBAL_GRP20 | Flush caused by thread GCT imbalance | 2 | Group 20 pm_flush1 |
| PM_DC_INV_L2_GRP20 | L1 D cache entries invalidated from L2 | 3 | Group 20 pm_flush1 |
| PM_INST_CMPL_GRP20 | Instructions completed | 4 | Group 20 pm_flush1 |
| PM_RUN_CYC_GRP20 | Run cycles | 5 | Group 20 pm_flush1 |
| PM_ITLB_MISS_GRP21 | Instruction TLB misses | 0 | Group 21 pm_flush2 |
| PM_IOPS_CMPL_GRP21 | IOPS instructions completed | 1 | Group 21 pm_flush2 |
| PM_FLUSH_SB_GRP21 | Flush caused by scoreboard operation | 2 | Group 21 pm_flush2 |
| PM_FLUSH_SYNC_GRP21 | Flush caused by sync | 3 | Group 21 pm_flush2 |
| PM_INST_CMPL_GRP21 | Instructions completed | 4 | Group 21 pm_flush2 |
| PM_RUN_CYC_GRP21 | Run cycles | 5 | Group 21 pm_flush2 |
| PM_LSU_FLUSH_SRQ_GRP22 | SRQ flushes | 0 | Group 22 pm_lsu_flush_srq_lrq |
| PM_LSU_FLUSH_LRQ_GRP22 | LRQ flushes | 1 | Group 22 pm_lsu_flush_srq_lrq |
| PM_IOPS_CMPL_GRP22 | IOPS instructions completed | 2 | Group 22 pm_lsu_flush_srq_lrq |
| PM_LSU_FLUSH_GRP22 | Flush initiated by LSU | 3 | Group 22 pm_lsu_flush_srq_lrq |
| PM_INST_CMPL_GRP22 | Instructions completed | 4 | Group 22 pm_lsu_flush_srq_lrq |
| PM_RUN_CYC_GRP22 | Run cycles | 5 | Group 22 pm_lsu_flush_srq_lrq |
| PM_LSU0_FLUSH_LRQ_GRP23 | LSU0 LRQ flushes | 0 | Group 23 pm_lsu_flush_lrq |
| PM_LSU1_FLUSH_LRQ_GRP23 | LSU1 LRQ flushes | 1 | Group 23 pm_lsu_flush_lrq |
| PM_LSU_FLUSH_GRP23 | Flush initiated by LSU | 2 | Group 23 pm_lsu_flush_lrq |
| PM_IOPS_CMPL_GRP23 | IOPS instructions completed | 3 | Group 23 pm_lsu_flush_lrq |
| PM_INST_CMPL_GRP23 | Instructions completed | 4 | Group 23 pm_lsu_flush_lrq |
| PM_RUN_CYC_GRP23 | Run cycles | 5 | Group 23 pm_lsu_flush_lrq |
| PM_LSU0_FLUSH_SRQ_GRP24 | LSU0 SRQ flushes | 0 | Group 24 pm_lsu_flush_srq |
| PM_LSU1_FLUSH_SRQ_GRP24 | LSU1 SRQ flushes | 1 | Group 24 pm_lsu_flush_srq |
| PM_IOPS_CMPL_GRP24 | IOPS instructions completed | 2 | Group 24 pm_lsu_flush_srq |
| PM_LSU_FLUSH_GRP24 | Flush initiated by LSU | 3 | Group 24 pm_lsu_flush_srq |
| PM_INST_CMPL_GRP24 | Instructions completed | 4 | Group 24 pm_lsu_flush_srq |
| PM_RUN_CYC_GRP24 | Run cycles | 5 | Group 24 pm_lsu_flush_srq |
| PM_LSU_FLUSH_ULD_GRP25 | LRQ unaligned load flushes | 0 | Group 25 pm_lsu_flush_unaligned |
| PM_LSU_FLUSH_UST_GRP25 | SRQ unaligned store flushes | 1 | Group 25 pm_lsu_flush_unaligned |
| PM_BR_ISSUED_GRP25 | Branches issued | 2 | Group 25 pm_lsu_flush_unaligned |
| PM_IOPS_CMPL_GRP25 | IOPS instructions completed | 3 | Group 25 pm_lsu_flush_unaligned |
| PM_INST_CMPL_GRP25 | Instructions completed | 4 | Group 25 pm_lsu_flush_unaligned |
| PM_RUN_CYC_GRP25 | Run cycles | 5 | Group 25 pm_lsu_flush_unaligned |
| PM_LSU0_FLUSH_ULD_GRP26 | LSU0 unaligned load flushes | 0 | Group 26 pm_lsu_flush_uld |
| PM_LSU1_FLUSH_ULD_GRP26 | LSU1 unaligned load flushes | 1 | Group 26 pm_lsu_flush_uld |
| PM_LSU_FLUSH_GRP26 | Flush initiated by LSU | 2 | Group 26 pm_lsu_flush_uld |
| PM_IOPS_CMPL_GRP26 | IOPS instructions completed | 3 | Group 26 pm_lsu_flush_uld |
| PM_INST_CMPL_GRP26 | Instructions completed | 4 | Group 26 pm_lsu_flush_uld |
| PM_RUN_CYC_GRP26 | Run cycles | 5 | Group 26 pm_lsu_flush_uld |
| PM_LSU0_FLUSH_UST_GRP27 | LSU0 unaligned store flushes | 0 | Group 27 pm_lsu_flush_ust |
| PM_LSU1_FLUSH_UST_GRP27 | LSU1 unaligned store flushes | 1 | Group 27 pm_lsu_flush_ust |
| PM_IOPS_CMPL_GRP27 | IOPS instructions completed | 2 | Group 27 pm_lsu_flush_ust |
| PM_LSU_FLUSH_GRP27 | Flush initiated by LSU | 3 | Group 27 pm_lsu_flush_ust |
| PM_INST_CMPL_GRP27 | Instructions completed | 4 | Group 27 pm_lsu_flush_ust |
| PM_RUN_CYC_GRP27 | Run cycles | 5 | Group 27 pm_lsu_flush_ust |
| PM_LSU_FLUSH_LRQ_FULL_GRP28 | Flush caused by LRQ full | 0 | Group 28 pm_lsu_flush_full |
| PM_IOPS_CMPL_GRP28 | IOPS instructions completed | 1 | Group 28 pm_lsu_flush_full |
| PM_MRK_LSU_FLUSH_LRQ_GRP28 | Marked LRQ flushes | 2 | Group 28 pm_lsu_flush_full |
| PM_LSU_FLUSH_SRQ_FULL_GRP28 | Flush caused by SRQ full | 3 | Group 28 pm_lsu_flush_full |
| PM_INST_CMPL_GRP28 | Instructions completed | 4 | Group 28 pm_lsu_flush_full |
| PM_RUN_CYC_GRP28 | Run cycles | 5 | Group 28 pm_lsu_flush_full |
| PM_GRP_MRK_GRP29 | Group marked in IDU | 0 | Group 29 pm_lsu_stall1 |
| PM_CMPLU_STALL_LSU_GRP29 | Completion stall caused by LSU instruction | 1 | Group 29 pm_lsu_stall1 |
| PM_IOPS_CMPL_GRP29 | IOPS instructions completed | 2 | Group 29 pm_lsu_stall1 |
| PM_CMPLU_STALL_REJECT_GRP29 | Completion stall caused by reject | 3 | Group 29 pm_lsu_stall1 |
| PM_INST_CMPL_GRP29 | Instructions completed | 4 | Group 29 pm_lsu_stall1 |
| PM_RUN_CYC_GRP29 | Run cycles | 5 | Group 29 pm_lsu_stall1 |
| PM_IOPS_CMPL_GRP30 | IOPS instructions completed | 0 | Group 30 pm_lsu_stall2 |
| PM_CMPLU_STALL_DCACHE_MISS_GRP30 | Completion stall caused by D cache miss | 1 | Group 30 pm_lsu_stall2 |
| PM_CYC_GRP30 | Processor cycles | 2 | Group 30 pm_lsu_stall2 |
| PM_CMPLU_STALL_ERAT_MISS_GRP30 | Completion stall caused by ERAT miss | 3 | Group 30 pm_lsu_stall2 |
| PM_INST_CMPL_GRP30 | Instructions completed | 4 | Group 30 pm_lsu_stall2 |
| PM_RUN_CYC_GRP30 | Run cycles | 5 | Group 30 pm_lsu_stall2 |
| PM_GRP_IC_MISS_BR_REDIR_NONSPEC_GRP31 | Group experienced non-speculative I cache miss or branch redirect | 0 | Group 31 pm_fxu_stall |
| PM_CMPLU_STALL_FXU_GRP31 | Completion stall caused by FXU instruction | 1 | Group 31 pm_fxu_stall |
| PM_IOPS_CMPL_GRP31 | IOPS instructions completed | 2 | Group 31 pm_fxu_stall |
| PM_CMPLU_STALL_DIV_GRP31 | Completion stall caused by DIV instruction | 3 | Group 31 pm_fxu_stall |
| PM_INST_CMPL_GRP31 | Instructions completed | 4 | Group 31 pm_fxu_stall |
| PM_RUN_CYC_GRP31 | Run cycles | 5 | Group 31 pm_fxu_stall |
| PM_FPU_FULL_CYC_GRP32 | Cycles FPU issue queue full | 0 | Group 32 pm_fpu_stall |
| PM_CMPLU_STALL_FDIV_GRP32 | Completion stall caused by FDIV or FQRT instruction | 1 | Group 32 pm_fpu_stall |
| PM_IOPS_CMPL_GRP32 | IOPS instructions completed | 2 | Group 32 pm_fpu_stall |
| PM_CMPLU_STALL_FPU_GRP32 | Completion stall caused by FPU instruction | 3 | Group 32 pm_fpu_stall |
| PM_INST_CMPL_GRP32 | Instructions completed | 4 | Group 32 pm_fpu_stall |
| PM_RUN_CYC_GRP32 | Run cycles | 5 | Group 32 pm_fpu_stall |
| PM_LARX_LSU0_GRP33 | Larx executed on LSU0 | 0 | Group 33 pm_queue_full |
| PM_BRQ_FULL_CYC_GRP33 | Cycles branch queue full | 1 | Group 33 pm_queue_full |
| PM_LSU_LRQ_FULL_CYC_GRP33 | Cycles LRQ full | 2 | Group 33 pm_queue_full |
| PM_LSU_LMQ_FULL_CYC_GRP33 | Cycles LMQ full | 3 | Group 33 pm_queue_full |
| PM_INST_CMPL_GRP33 | Instructions completed | 4 | Group 33 pm_queue_full |
| PM_RUN_CYC_GRP33 | Run cycles | 5 | Group 33 pm_queue_full |
| PM_FPU0_FULL_CYC_GRP34 | Cycles FPU0 issue queue full | 0 | Group 34 pm_issueq_full |
| PM_FPU1_FULL_CYC_GRP34 | Cycles FPU1 issue queue full | 1 | Group 34 pm_issueq_full |
| PM_FXLS0_FULL_CYC_GRP34 | Cycles FXU0/LS0 queue full | 2 | Group 34 pm_issueq_full |
| PM_FXLS1_FULL_CYC_GRP34 | Cycles FXU1/LS1 queue full | 3 | Group 34 pm_issueq_full |
| PM_INST_CMPL_GRP34 | Instructions completed | 4 | Group 34 pm_issueq_full |
| PM_RUN_CYC_GRP34 | Run cycles | 5 | Group 34 pm_issueq_full |
| PM_CR_MAP_FULL_CYC_GRP35 | Cycles CR logical operation mapper full | 0 | Group 35 pm_mapper_full1 |
| PM_LR_CTR_MAP_FULL_CYC_GRP35 | Cycles LR/CTR mapper full | 1 | Group 35 pm_mapper_full1 |
| PM_GPR_MAP_FULL_CYC_GRP35 | Cycles GPR mapper full | 2 | Group 35 pm_mapper_full1 |
| PM_CRQ_FULL_CYC_GRP35 | Cycles CR issue queue full | 3 | Group 35 pm_mapper_full1 |
| PM_INST_CMPL_GRP35 | Instructions completed | 4 | Group 35 pm_mapper_full1 |
| PM_RUN_CYC_GRP35 | Run cycles | 5 | Group 35 pm_mapper_full1 |
| PM_FPR_MAP_FULL_CYC_GRP36 | Cycles FPR mapper full | 0 | Group 36 pm_mapper_full2 |
| PM_XER_MAP_FULL_CYC_GRP36 | Cycles XER mapper full | 1 | Group 36 pm_mapper_full2 |
| PM_MRK_DATA_FROM_L2MISS_GRP36 | Marked data loaded missed L2 | 2 | Group 36 pm_mapper_full2 |
| PM_IOPS_CMPL_GRP36 | IOPS instructions completed | 3 | Group 36 pm_mapper_full2 |
| PM_INST_CMPL_GRP36 | Instructions completed | 4 | Group 36 pm_mapper_full2 |
| PM_RUN_CYC_GRP36 | Run cycles | 5 | Group 36 pm_mapper_full2 |
| PM_STCX_FAIL_GRP37 | STCX failed | 0 | Group 37 pm_misc_load |
| PM_STCX_PASS_GRP37 | Stcx passes | 1 | Group 37 pm_misc_load |
| PM_LSU0_NCLD_GRP37 | LSU0 non-cacheable loads | 2 | Group 37 pm_misc_load |
| PM_LSU1_NCLD_GRP37 | LSU1 non-cacheable loads | 3 | Group 37 pm_misc_load |
| PM_INST_CMPL_GRP37 | Instructions completed | 4 | Group 37 pm_misc_load |
| PM_RUN_CYC_GRP37 | Run cycles | 5 | Group 37 pm_misc_load |
| PM_LSU0_BUSY_REJECT_GRP38 | LSU0 busy due to reject | 0 | Group 38 pm_ic_demand |
| PM_LSU1_BUSY_REJECT_GRP38 | LSU1 busy due to reject | 1 | Group 38 pm_ic_demand |
| PM_IC_DEMAND_L2_BHT_REDIRECT_GRP38 | L2 I cache demand request due to BHT redirect | 2 | Group 38 pm_ic_demand |
| PM_IC_DEMAND_L2_BR_REDIRECT_GRP38 | L2 I cache demand request due to branch redirect | 3 | Group 38 pm_ic_demand |
| PM_INST_CMPL_GRP38 | Instructions completed | 4 | Group 38 pm_ic_demand |
| PM_RUN_CYC_GRP38 | Run cycles | 5 | Group 38 pm_ic_demand |
| PM_IERAT_XLATE_WR_GRP39 | Translation written to ierat | 0 | Group 39 pm_ic_pref |
| PM_IC_PREF_REQ_GRP39 | Instruction prefetch requests | 1 | Group 39 pm_ic_pref |
| PM_IC_PREF_INSTALL_GRP39 | Instruction prefetched installed in prefetch | 2 | Group 39 pm_ic_pref |
| PM_0INST_FETCH_GRP39 | No instructions fetched | 3 | Group 39 pm_ic_pref |
| PM_INST_CMPL_GRP39 | Instructions completed | 4 | Group 39 pm_ic_pref |
| PM_RUN_CYC_GRP39 | Run cycles | 5 | Group 39 pm_ic_pref |
| PM_GRP_IC_MISS_NONSPEC_GRP40 | Group experienced non-speculative I cache miss | 0 | Group 40 pm_ic_miss |
| PM_GRP_IC_MISS_GRP40 | Group experienced I cache miss | 1 | Group 40 pm_ic_miss |
| PM_L1_DCACHE_RELOAD_VALID_GRP40 | L1 reload data source valid | 2 | Group 40 pm_ic_miss |
| PM_IOPS_CMPL_GRP40 | IOPS instructions completed | 3 | Group 40 pm_ic_miss |
| PM_INST_CMPL_GRP40 | Instructions completed | 4 | Group 40 pm_ic_miss |
| PM_RUN_CYC_GRP40 | Run cycles | 5 | Group 40 pm_ic_miss |
| PM_TLB_MISS_GRP41 | TLB misses | 0 | Group 41 pm_branch_miss |
| PM_SLB_MISS_GRP41 | SLB misses | 1 | Group 41 pm_branch_miss |
| PM_BR_MPRED_CR_GRP41 | Branch mispredictions due to CR bit setting | 2 | Group 41 pm_branch_miss |
| PM_BR_MPRED_TA_GRP41 | Branch mispredictions due to target address | 3 | Group 41 pm_branch_miss |
| PM_INST_CMPL_GRP41 | Instructions completed | 4 | Group 41 pm_branch_miss |
| PM_RUN_CYC_GRP41 | Run cycles | 5 | Group 41 pm_branch_miss |
| PM_BR_UNCOND_GRP42 | Unconditional branch | 0 | Group 42 pm_branch1 |
| PM_BR_PRED_TA_GRP42 | A conditional branch was predicted, target prediction | 1 | Group 42 pm_branch1 |
| PM_BR_PRED_CR_GRP42 | A conditional branch was predicted, CR prediction | 2 | Group 42 pm_branch1 |
| PM_BR_PRED_CR_TA_GRP42 | A conditional branch was predicted, CR and target prediction | 3 | Group 42 pm_branch1 |
| PM_INST_CMPL_GRP42 | Instructions completed | 4 | Group 42 pm_branch1 |
| PM_RUN_CYC_GRP42 | Run cycles | 5 | Group 42 pm_branch1 |
| PM_GRP_BR_REDIR_NONSPEC_GRP43 | Group experienced non-speculative branch redirect | 0 | Group 43 pm_branch2 |
| PM_GRP_BR_REDIR_GRP43 | Group experienced branch redirect | 1 | Group 43 pm_branch2 |
| PM_FLUSH_BR_MPRED_GRP43 | Flush caused by branch mispredict | 2 | Group 43 pm_branch2 |
| PM_IOPS_CMPL_GRP43 | IOPS instructions completed | 3 | Group 43 pm_branch2 |
| PM_INST_CMPL_GRP43 | Instructions completed | 4 | Group 43 pm_branch2 |
| PM_RUN_CYC_GRP43 | Run cycles | 5 | Group 43 pm_branch2 |
| PM_DATA_TABLEWALK_CYC_GRP44 | Cycles doing data tablewalks | 0 | Group 44 pm_L1_tlbmiss |
| PM_DTLB_MISS_GRP44 | Data TLB misses | 1 | Group 44 pm_L1_tlbmiss |
| PM_LD_MISS_L1_GRP44 | L1 D cache load misses | 2 | Group 44 pm_L1_tlbmiss |
| PM_LD_REF_L1_GRP44 | L1 D cache load references | 3 | Group 44 pm_L1_tlbmiss |
| PM_INST_CMPL_GRP44 | Instructions completed | 4 | Group 44 pm_L1_tlbmiss |
| PM_RUN_CYC_GRP44 | Run cycles | 5 | Group 44 pm_L1_tlbmiss |
| PM_DATA_FROM_L2_GRP45 | Data loaded from L2 | 0 | Group 45 pm_L1_DERAT_miss |
| PM_LSU_DERAT_MISS_GRP45 | DERAT misses | 1 | Group 45 pm_L1_DERAT_miss |
| PM_ST_REF_L1_GRP45 | L1 D cache store references | 2 | Group 45 pm_L1_DERAT_miss |
| PM_ST_MISS_L1_GRP45 | L1 D cache store misses | 3 | Group 45 pm_L1_DERAT_miss |
| PM_INST_CMPL_GRP45 | Instructions completed | 4 | Group 45 pm_L1_DERAT_miss |
| PM_RUN_CYC_GRP45 | Run cycles | 5 | Group 45 pm_L1_DERAT_miss |
| PM_DSLB_MISS_GRP46 | Data SLB misses | 0 | Group 46 pm_L1_slbmiss |
| PM_ISLB_MISS_GRP46 | Instruction SLB misses | 1 | Group 46 pm_L1_slbmiss |
| PM_LD_MISS_L1_LSU0_GRP46 | LSU0 L1 D cache load misses | 2 | Group 46 pm_L1_slbmiss |
| PM_LD_MISS_L1_LSU1_GRP46 | LSU1 L1 D cache load misses | 3 | Group 46 pm_L1_slbmiss |
| PM_INST_CMPL_GRP46 | Instructions completed | 4 | Group 46 pm_L1_slbmiss |
| PM_RUN_CYC_GRP46 | Run cycles | 5 | Group 46 pm_L1_slbmiss |
| PM_DTLB_REF_4K_GRP47 | Data TLB reference for 4K page | 0 | Group 47 pm_L1_dtlbmiss_4K |
| PM_DTLB_MISS_4K_GRP47 | Data TLB miss for 4K page | 1 | Group 47 pm_L1_dtlbmiss_4K |
| PM_LD_REF_L1_LSU0_GRP47 | LSU0 L1 D cache load references | 2 | Group 47 pm_L1_dtlbmiss_4K |
| PM_LD_REF_L1_LSU1_GRP47 | LSU1 L1 D cache load references | 3 | Group 47 pm_L1_dtlbmiss_4K |
| PM_INST_CMPL_GRP47 | Instructions completed | 4 | Group 47 pm_L1_dtlbmiss_4K |
| PM_RUN_CYC_GRP47 | Run cycles | 5 | Group 47 pm_L1_dtlbmiss_4K |
| PM_DTLB_REF_16M_GRP48 | Data TLB reference for 16M page | 0 | Group 48 pm_L1_dtlbmiss_16M |
| PM_DTLB_MISS_16M_GRP48 | Data TLB miss for 16M page | 1 | Group 48 pm_L1_dtlbmiss_16M |
| PM_ST_REF_L1_LSU0_GRP48 | LSU0 L1 D cache store references | 2 | Group 48 pm_L1_dtlbmiss_16M |
| PM_ST_REF_L1_LSU1_GRP48 | LSU1 L1 D cache store references | 3 | Group 48 pm_L1_dtlbmiss_16M |
| PM_INST_CMPL_GRP48 | Instructions completed | 4 | Group 48 pm_L1_dtlbmiss_16M |
| PM_RUN_CYC_GRP48 | Run cycles | 5 | Group 48 pm_L1_dtlbmiss_16M |
| PM_DATA_FROM_L3_GRP49 | Data loaded from L3 | 0 | Group 49 pm_dsource1 |
| PM_DATA_FROM_LMEM_GRP49 | Data loaded from local memory | 1 | Group 49 pm_dsource1 |
| PM_FLUSH_GRP49 | Flushes | 2 | Group 49 pm_dsource1 |
| PM_IOPS_CMPL_GRP49 | IOPS instructions completed | 3 | Group 49 pm_dsource1 |
| PM_INST_CMPL_GRP49 | Instructions completed | 4 | Group 49 pm_dsource1 |
| PM_RUN_CYC_GRP49 | Run cycles | 5 | Group 49 pm_dsource1 |
| PM_DATA_FROM_L3_GRP50 | Data loaded from L3 | 0 | Group 50 pm_dsource2 |
| PM_DATA_FROM_LMEM_GRP50 | Data loaded from local memory | 1 | Group 50 pm_dsource2 |
| PM_DATA_FROM_L2MISS_GRP50 | Data loaded missed L2 | 2 | Group 50 pm_dsource2 |
| PM_DATA_FROM_RMEM_GRP50 | Data loaded from remote memory | 3 | Group 50 pm_dsource2 |
| PM_INST_CMPL_GRP50 | Instructions completed | 4 | Group 50 pm_dsource2 |
| PM_RUN_CYC_GRP50 | Run cycles | 5 | Group 50 pm_dsource2 |
| PM_DATA_FROM_L25_SHR_GRP51 | Data loaded from L2.5 shared | 0 | Group 51 pm_dsource_L2 |
| PM_DATA_FROM_L25_MOD_GRP51 | Data loaded from L2.5 modified | 1 | Group 51 pm_dsource_L2 |
| PM_DATA_FROM_L275_SHR_GRP51 | Data loaded from L2.75 shared | 2 | Group 51 pm_dsource_L2 |
| PM_DATA_FROM_L275_MOD_GRP51 | Data loaded from L2.75 modified | 3 | Group 51 pm_dsource_L2 |
| PM_INST_CMPL_GRP51 | Instructions completed | 4 | Group 51 pm_dsource_L2 |
| PM_RUN_CYC_GRP51 | Run cycles | 5 | Group 51 pm_dsource_L2 |
| PM_DATA_FROM_L35_SHR_GRP52 | Data loaded from L3.5 shared | 0 | Group 52 pm_dsource_L3 |
| PM_DATA_FROM_L35_MOD_GRP52 | Data loaded from L3.5 modified | 1 | Group 52 pm_dsource_L3 |
| PM_DATA_FROM_L375_SHR_GRP52 | Data loaded from L3.75 shared | 2 | Group 52 pm_dsource_L3 |
| PM_DATA_FROM_L375_MOD_GRP52 | Data loaded from L3.75 modified | 3 | Group 52 pm_dsource_L3 |
| PM_INST_CMPL_GRP52 | Instructions completed | 4 | Group 52 pm_dsource_L3 |
| PM_RUN_CYC_GRP52 | Run cycles | 5 | Group 52 pm_dsource_L3 |
| PM_INST_FROM_L3_GRP53 | Instruction fetched from L3 | 0 | Group 53 pm_isource1 |
| PM_INST_FROM_L1_GRP53 | Instruction fetched from L1 | 1 | Group 53 pm_isource1 |
| PM_INST_FROM_PREF_GRP53 | Instructions fetched from prefetch | 2 | Group 53 pm_isource1 |
| PM_INST_FROM_RMEM_GRP53 | Instruction fetched from remote memory | 3 | Group 53 pm_isource1 |
| PM_INST_CMPL_GRP53 | Instructions completed | 4 | Group 53 pm_isource1 |
| PM_RUN_CYC_GRP53 | Run cycles | 5 | Group 53 pm_isource1 |
| PM_INST_FROM_L2_GRP54 | Instructions fetched from L2 | 0 | Group 54 pm_isource2 |
| PM_INST_FROM_LMEM_GRP54 | Instruction fetched from local memory | 1 | Group 54 pm_isource2 |
| PM_IOPS_CMPL_GRP54 | IOPS instructions completed | 2 | Group 54 pm_isource2 |
| PM_0INST_FETCH_GRP54 | No instructions fetched | 3 | Group 54 pm_isource2 |
| PM_INST_CMPL_GRP54 | Instructions completed | 4 | Group 54 pm_isource2 |
| PM_RUN_CYC_GRP54 | Run cycles | 5 | Group 54 pm_isource2 |
| PM_INST_FROM_L25_SHR_GRP55 | Instruction fetched from L2.5 shared | 0 | Group 55 pm_isource_L2 |
| PM_INST_FROM_L25_MOD_GRP55 | Instruction fetched from L2.5 modified | 1 | Group 55 pm_isource_L2 |
| PM_INST_FROM_L275_SHR_GRP55 | Instruction fetched from L2.75 shared | 2 | Group 55 pm_isource_L2 |
| PM_INST_FROM_L275_MOD_GRP55 | Instruction fetched from L2.75 modified | 3 | Group 55 pm_isource_L2 |
| PM_INST_CMPL_GRP55 | Instructions completed | 4 | Group 55 pm_isource_L2 |
| PM_RUN_CYC_GRP55 | Run cycles | 5 | Group 55 pm_isource_L2 |
| PM_INST_FROM_L35_SHR_GRP56 | Instruction fetched from L3.5 shared | 0 | Group 56 pm_isource_L3 |
| PM_INST_FROM_L35_MOD_GRP56 | Instruction fetched from L3.5 modified | 1 | Group 56 pm_isource_L3 |
| PM_INST_FROM_L375_SHR_GRP56 | Instruction fetched from L3.75 shared | 2 | Group 56 pm_isource_L3 |
| PM_INST_FROM_L375_MOD_GRP56 | Instruction fetched from L3.75 modified | 3 | Group 56 pm_isource_L3 |
| PM_INST_CMPL_GRP56 | Instructions completed | 4 | Group 56 pm_isource_L3 |
| PM_RUN_CYC_GRP56 | Run cycles | 5 | Group 56 pm_isource_L3 |
| PM_PTEG_FROM_L25_SHR_GRP57 | PTEG loaded from L2.5 shared | 0 | Group 57 pm_pteg_source1 |
| PM_PTEG_FROM_L25_MOD_GRP57 | PTEG loaded from L2.5 modified | 1 | Group 57 pm_pteg_source1 |
| PM_PTEG_FROM_L275_SHR_GRP57 | PTEG loaded from L2.75 shared | 2 | Group 57 pm_pteg_source1 |
| PM_PTEG_FROM_L275_MOD_GRP57 | PTEG loaded from L2.75 modified | 3 | Group 57 pm_pteg_source1 |
| PM_INST_CMPL_GRP57 | Instructions completed | 4 | Group 57 pm_pteg_source1 |
| PM_RUN_CYC_GRP57 | Run cycles | 5 | Group 57 pm_pteg_source1 |
| PM_PTEG_FROM_L35_SHR_GRP58 | PTEG loaded from L3.5 shared | 0 | Group 58 pm_pteg_source2 |
| PM_PTEG_FROM_L35_MOD_GRP58 | PTEG loaded from L3.5 modified | 1 | Group 58 pm_pteg_source2 |
| PM_PTEG_FROM_L375_SHR_GRP58 | PTEG loaded from L3.75 shared | 2 | Group 58 pm_pteg_source2 |
| PM_PTEG_FROM_L375_MOD_GRP58 | PTEG loaded from L3.75 modified | 3 | Group 58 pm_pteg_source2 |
| PM_INST_CMPL_GRP58 | Instructions completed | 4 | Group 58 pm_pteg_source2 |
| PM_RUN_CYC_GRP58 | Run cycles | 5 | Group 58 pm_pteg_source2 |
| PM_PTEG_FROM_L2_GRP59 | PTEG loaded from L2 | 0 | Group 59 pm_pteg_source3 |
| PM_PTEG_FROM_LMEM_GRP59 | PTEG loaded from local memory | 1 | Group 59 pm_pteg_source3 |
| PM_PTEG_FROM_L2MISS_GRP59 | PTEG loaded from L2 miss | 2 | Group 59 pm_pteg_source3 |
| PM_PTEG_FROM_RMEM_GRP59 | PTEG loaded from remote memory | 3 | Group 59 pm_pteg_source3 |
| PM_INST_CMPL_GRP59 | Instructions completed | 4 | Group 59 pm_pteg_source3 |
| PM_RUN_CYC_GRP59 | Run cycles | 5 | Group 59 pm_pteg_source3 |
| PM_PTEG_FROM_L3_GRP60 | PTEG loaded from L3 | 0 | Group 60 pm_pteg_source4 |
| PM_GRP_DISP_GRP60 | Group dispatches | 1 | Group 60 pm_pteg_source4 |
| PM_GRP_DISP_SUCCESS_GRP60 | Group dispatch success | 2 | Group 60 pm_pteg_source4 |
| PM_DC_INV_L2_GRP60 | L1 D cache entries invalidated from L2 | 3 | Group 60 pm_pteg_source4 |
| PM_INST_CMPL_GRP60 | Instructions completed | 4 | Group 60 pm_pteg_source4 |
| PM_RUN_CYC_GRP60 | Run cycles | 5 | Group 60 pm_pteg_source4 |
| PM_L2SA_RCLD_DISP_GRP61 | L2 Slice A RC load dispatch attempt | 0 | Group 61 pm_L2SA_ld |
| PM_L2SA_RCLD_DISP_FAIL_RC_FULL_GRP61 | L2 Slice A RC load dispatch attempt failed due to all RC full | 1 | Group 61 pm_L2SA_ld |
| PM_L2SA_RCLD_DISP_FAIL_ADDR_GRP61 | L2 Slice A RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ | 2 | Group 61 pm_L2SA_ld |
| PM_L2SA_RCLD_DISP_FAIL_OTHER_GRP61 | L2 Slice A RC load dispatch attempt failed due to other reasons | 3 | Group 61 pm_L2SA_ld |
| PM_INST_CMPL_GRP61 | Instructions completed | 4 | Group 61 pm_L2SA_ld |
| PM_RUN_CYC_GRP61 | Run cycles | 5 | Group 61 pm_L2SA_ld |
| PM_L2SA_RCST_DISP_GRP62 | L2 Slice A RC store dispatch attempt | 0 | Group 62 pm_L2SA_st |
| PM_L2SA_RCST_DISP_FAIL_RC_FULL_GRP62 | L2 Slice A RC store dispatch attempt failed due to all RC full | 1 | Group 62 pm_L2SA_st |
| PM_L2SA_RCST_DISP_FAIL_ADDR_GRP62 | L2 Slice A RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ | 2 | Group 62 pm_L2SA_st |
| PM_L2SA_RCST_DISP_FAIL_OTHER_GRP62 | L2 Slice A RC store dispatch attempt failed due to other reasons | 3 | Group 62 pm_L2SA_st |
| PM_INST_CMPL_GRP62 | Instructions completed | 4 | Group 62 pm_L2SA_st |
| PM_RUN_CYC_GRP62 | Run cycles | 5 | Group 62 pm_L2SA_st |
| PM_L2SA_RC_DISP_FAIL_CO_BUSY_GRP63 | L2 Slice A RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy | 0 | Group 63 pm_L2SA_st2 |
| PM_L2SA_ST_REQ_GRP63 | L2 slice A store requests | 1 | Group 63 pm_L2SA_st2 |
| PM_L2SA_RC_DISP_FAIL_CO_BUSY_ALL_GRP63 | L2 Slice A RC dispatch attempt failed due to all CO busy | 2 | Group 63 pm_L2SA_st2 |
| PM_L2SA_ST_HIT_GRP63 | L2 slice A store hits | 3 | Group 63 pm_L2SA_st2 |
| PM_INST_CMPL_GRP63 | Instructions completed | 4 | Group 63 pm_L2SA_st2 |
| PM_RUN_CYC_GRP63 | Run cycles | 5 | Group 63 pm_L2SA_st2 |
| PM_L2SB_RCLD_DISP_GRP64 | L2 Slice B RC load dispatch attempt | 0 | Group 64 pm_L2SB_ld |
| PM_L2SB_RCLD_DISP_FAIL_RC_FULL_GRP64 | L2 Slice B RC load dispatch attempt failed due to all RC full | 1 | Group 64 pm_L2SB_ld |
| PM_L2SB_RCLD_DISP_FAIL_ADDR_GRP64 | L2 Slice B RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ | 2 | Group 64 pm_L2SB_ld |
| PM_L2SB_RCLD_DISP_FAIL_OTHER_GRP64 | L2 Slice B RC load dispatch attempt failed due to other reasons | 3 | Group 64 pm_L2SB_ld |
| PM_INST_CMPL_GRP64 | Instructions completed | 4 | Group 64 pm_L2SB_ld |
| PM_RUN_CYC_GRP64 | Run cycles | 5 | Group 64 pm_L2SB_ld |
| PM_L2SB_RCST_DISP_GRP65 | L2 Slice B RC store dispatch attempt | 0 | Group 65 pm_L2SB_st |
| PM_L2SB_RCST_DISP_FAIL_RC_FULL_GRP65 | L2 Slice B RC store dispatch attempt failed due to all RC full | 1 | Group 65 pm_L2SB_st |
| PM_L2SB_RCST_DISP_FAIL_ADDR_GRP65 | L2 Slice B RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ | 2 | Group 65 pm_L2SB_st |
| PM_L2SB_RCST_DISP_FAIL_OTHER_GRP65 | L2 Slice B RC store dispatch attempt failed due to other reasons | 3 | Group 65 pm_L2SB_st |
| PM_INST_CMPL_GRP65 | Instructions completed | 4 | Group 65 pm_L2SB_st |
| PM_RUN_CYC_GRP65 | Run cycles | 5 | Group 65 pm_L2SB_st |
| PM_L2SB_RC_DISP_FAIL_CO_BUSY_GRP66 | L2 Slice B RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy | 0 | Group 66 pm_L2SB_st2 |
| PM_L2SB_ST_REQ_GRP66 | L2 slice B store requests | 1 | Group 66 pm_L2SB_st2 |
| PM_L2SB_RC_DISP_FAIL_CO_BUSY_ALL_GRP66 | L2 Slice B RC dispatch attempt failed due to all CO busy | 2 | Group 66 pm_L2SB_st2 |
| PM_L2SB_ST_HIT_GRP66 | L2 slice B store hits | 3 | Group 66 pm_L2SB_st2 |
| PM_INST_CMPL_GRP66 | Instructions completed | 4 | Group 66 pm_L2SB_st2 |
| PM_RUN_CYC_GRP66 | Run cycles | 5 | Group 66 pm_L2SB_st2 |
| PM_L2SC_RCLD_DISP_GRP67 | L2 Slice C RC load dispatch attempt | 0 | Group 67 pm_L2SB_ld |
| PM_L2SC_RCLD_DISP_FAIL_RC_FULL_GRP67 | L2 Slice C RC load dispatch attempt failed due to all RC full | 1 | Group 67 pm_L2SB_ld |
| PM_L2SC_RCLD_DISP_FAIL_ADDR_GRP67 | L2 Slice C RC load dispatch attempt failed due to address collision with RC/CO/SN/SQ | 2 | Group 67 pm_L2SB_ld |
| PM_L2SC_RCLD_DISP_FAIL_OTHER_GRP67 | L2 Slice C RC load dispatch attempt failed due to other reasons | 3 | Group 67 pm_L2SB_ld |
| PM_INST_CMPL_GRP67 | Instructions completed | 4 | Group 67 pm_L2SB_ld |
| PM_RUN_CYC_GRP67 | Run cycles | 5 | Group 67 pm_L2SB_ld |
| PM_L2SC_RCST_DISP_GRP68 | L2 Slice C RC store dispatch attempt | 0 | Group 68 pm_L2SB_st |
| PM_L2SC_RCST_DISP_FAIL_RC_FULL_GRP68 | L2 Slice C RC store dispatch attempt failed due to all RC full | 1 | Group 68 pm_L2SB_st |
| PM_L2SC_RCST_DISP_FAIL_ADDR_GRP68 | L2 Slice C RC store dispatch attempt failed due to address collision with RC/CO/SN/SQ | 2 | Group 68 pm_L2SB_st |
| PM_L2SC_RCST_DISP_FAIL_OTHER_GRP68 | L2 Slice C RC store dispatch attempt failed due to other reasons | 3 | Group 68 pm_L2SB_st |
| PM_INST_CMPL_GRP68 | Instructions completed | 4 | Group 68 pm_L2SB_st |
| PM_RUN_CYC_GRP68 | Run cycles | 5 | Group 68 pm_L2SB_st |
| PM_L2SC_RC_DISP_FAIL_CO_BUSY_GRP69 | L2 Slice C RC dispatch attempt failed due to RC/CO pair chosen was miss and CO already busy | 0 | Group 69 pm_L2SB_st2 |
| PM_L2SC_ST_REQ_GRP69 | L2 slice C store requests | 1 | Group 69 pm_L2SB_st2 |
| PM_L2SC_RC_DISP_FAIL_CO_BUSY_ALL_GRP69 | L2 Slice C RC dispatch attempt failed due to all CO busy | 2 | Group 69 pm_L2SB_st2 |
| PM_L2SC_ST_HIT_GRP69 | L2 slice C store hits | 3 | Group 69 pm_L2SB_st2 |
| PM_INST_CMPL_GRP69 | Instructions completed | 4 | Group 69 pm_L2SB_st2 |
| PM_RUN_CYC_GRP69 | Run cycles | 5 | Group 69 pm_L2SB_st2 |
| PM_L3SA_MOD_TAG_GRP70 | L3 slice A transition from modified to TAG | 0 | Group 70 pm_L3SA_trans |
| PM_IOPS_CMPL_GRP70 | IOPS instructions completed | 1 | Group 70 pm_L3SA_trans |
| PM_L3SA_MOD_INV_GRP70 | L3 slice A transition from modified to invalid | 2 | Group 70 pm_L3SA_trans |
| PM_L3SA_SHR_INV_GRP70 | L3 slice A transition from shared to invalid | 3 | Group 70 pm_L3SA_trans |
| PM_INST_CMPL_GRP70 | Instructions completed | 4 | Group 70 pm_L3SA_trans |
| PM_RUN_CYC_GRP70 | Run cycles | 5 | Group 70 pm_L3SA_trans |
| PM_IOPS_CMPL_GRP71 | IOPS instructions completed | 0 | Group 71 pm_L3SB_trans |
| PM_L3SB_MOD_TAG_GRP71 | L3 slice B transition from modified to TAG | 1 | Group 71 pm_L3SB_trans |
| PM_L3SB_MOD_INV_GRP71 | L3 slice B transition from modified to invalid | 2 | Group 71 pm_L3SB_trans |
| PM_L3SB_SHR_INV_GRP71 | L3 slice B transition from shared to invalid | 3 | Group 71 pm_L3SB_trans |
| PM_INST_CMPL_GRP71 | Instructions completed | 4 | Group 71 pm_L3SB_trans |
| PM_RUN_CYC_GRP71 | Run cycles | 5 | Group 71 pm_L3SB_trans |
| PM_IOPS_CMPL_GRP72 | IOPS instructions completed | 0 | Group 72 pm_L3SC_trans |
| PM_L3SC_MOD_TAG_GRP72 | L3 slice C transition from modified to TAG | 1 | Group 72 pm_L3SC_trans |
| PM_L3SC_MOD_INV_GRP72 | L3 slice C transition from modified to invalid | 2 | Group 72 pm_L3SC_trans |
| PM_L3SC_SHR_INV_GRP72 | L3 slice C transition from shared to invalid | 3 | Group 72 pm_L3SC_trans |
| PM_INST_CMPL_GRP72 | Instructions completed | 4 | Group 72 pm_L3SC_trans |
| PM_RUN_CYC_GRP72 | Run cycles | 5 | Group 72 pm_L3SC_trans |
| PM_L2SA_MOD_TAG_GRP73 | L2 slice A transition from modified to tagged | 0 | Group 73 pm_L2SA_trans |
| PM_L2SA_SHR_MOD_GRP73 | L2 slice A transition from shared to modified | 1 | Group 73 pm_L2SA_trans |
| PM_L2SA_MOD_INV_GRP73 | L2 slice A transition from modified to invalid | 2 | Group 73 pm_L2SA_trans |
| PM_L2SA_SHR_INV_GRP73 | L2 slice A transition from shared to invalid | 3 | Group 73 pm_L2SA_trans |
| PM_INST_CMPL_GRP73 | Instructions completed | 4 | Group 73 pm_L2SA_trans |
| PM_RUN_CYC_GRP73 | Run cycles | 5 | Group 73 pm_L2SA_trans |
| PM_L2SB_MOD_TAG_GRP74 | L2 slice B transition from modified to tagged | 0 | Group 74 pm_L2SB_trans |
| PM_L2SB_SHR_MOD_GRP74 | L2 slice B transition from shared to modified | 1 | Group 74 pm_L2SB_trans |
| PM_L2SB_MOD_INV_GRP74 | L2 slice B transition from modified to invalid | 2 | Group 74 pm_L2SB_trans |
| PM_L2SB_SHR_INV_GRP74 | L2 slice B transition from shared to invalid | 3 | Group 74 pm_L2SB_trans |
| PM_INST_CMPL_GRP74 | Instructions completed | 4 | Group 74 pm_L2SB_trans |
| PM_RUN_CYC_GRP74 | Run cycles | 5 | Group 74 pm_L2SB_trans |
| PM_L2SC_MOD_TAG_GRP75 | L2 slice C transition from modified to tagged | 0 | Group 75 pm_L2SC_trans |
| PM_L2SC_SHR_MOD_GRP75 | L2 slice C transition from shared to modified | 1 | Group 75 pm_L2SC_trans |
| PM_L2SC_MOD_INV_GRP75 | L2 slice C transition from modified to invalid | 2 | Group 75 pm_L2SC_trans |
| PM_L2SC_SHR_INV_GRP75 | L2 slice C transition from shared to invalid | 3 | Group 75 pm_L2SC_trans |
| PM_INST_CMPL_GRP75 | Instructions completed | 4 | Group 75 pm_L2SC_trans |
| PM_RUN_CYC_GRP75 | Run cycles | 5 | Group 75 pm_L2SC_trans |
| PM_L3SA_ALL_BUSY_GRP76 | L3 slice A active for every cycle all CI/CO machines busy | 0 | Group 76 pm_L3SAB_retry |
| PM_L3SB_ALL_BUSY_GRP76 | L3 slice B active for every cycle all CI/CO machines busy | 1 | Group 76 pm_L3SAB_retry |
| PM_L3SA_SNOOP_RETRY_GRP76 | L3 slice A snoop retries | 2 | Group 76 pm_L3SAB_retry |
| PM_L3SB_SNOOP_RETRY_GRP76 | L3 slice B snoop retries | 3 | Group 76 pm_L3SAB_retry |
| PM_INST_CMPL_GRP76 | Instructions completed | 4 | Group 76 pm_L3SAB_retry |
| PM_RUN_CYC_GRP76 | Run cycles | 5 | Group 76 pm_L3SAB_retry |
| PM_L3SA_REF_GRP77 | L3 slice A references | 0 | Group 77 pm_L3SAB_hit |
| PM_L3SB_REF_GRP77 | L3 slice B references | 1 | Group 77 pm_L3SAB_hit |
| PM_L3SA_HIT_GRP77 | L3 slice A hits | 2 | Group 77 pm_L3SAB_hit |
| PM_L3SB_HIT_GRP77 | L3 slice B hits | 3 | Group 77 pm_L3SAB_hit |
| PM_INST_CMPL_GRP77 | Instructions completed | 4 | Group 77 pm_L3SAB_hit |
| PM_RUN_CYC_GRP77 | Run cycles | 5 | Group 77 pm_L3SAB_hit |
| PM_L3SC_ALL_BUSY_GRP78 | L3 slice C active for every cycle all CI/CO machines busy | 0 | Group 78 pm_L3SC_retry_hit |
| PM_L3SC_REF_GRP78 | L3 slice C references | 1 | Group 78 pm_L3SC_retry_hit |
| PM_L3SC_SNOOP_RETRY_GRP78 | L3 slice C snoop retries | 2 | Group 78 pm_L3SC_retry_hit |
| PM_L3SC_HIT_GRP78 | L3 Slice C hits | 3 | Group 78 pm_L3SC_retry_hit |
| PM_INST_CMPL_GRP78 | Instructions completed | 4 | Group 78 pm_L3SC_retry_hit |
| PM_RUN_CYC_GRP78 | Run cycles | 5 | Group 78 pm_L3SC_retry_hit |
| PM_FPU_FDIV_GRP79 | FPU executed FDIV instruction | 0 | Group 79 pm_fpu1 |
| PM_FPU_FMA_GRP79 | FPU executed multiply-add instruction | 1 | Group 79 pm_fpu1 |
| PM_FPU_FMOV_FEST_GRP79 | FPU executing FMOV or FEST instructions | 2 | Group 79 pm_fpu1 |
| PM_FPU_FEST_GRP79 | FPU executed FEST instruction | 3 | Group 79 pm_fpu1 |
| PM_INST_CMPL_GRP79 | Instructions completed | 4 | Group 79 pm_fpu1 |
| PM_RUN_CYC_GRP79 | Run cycles | 5 | Group 79 pm_fpu1 |
| PM_FPU_1FLOP_GRP80 | FPU executed one flop instruction | 0 | Group 80 pm_fpu2 |
| PM_FPU_FSQRT_GRP80 | FPU executed FSQRT instruction | 1 | Group 80 pm_fpu2 |
| PM_FPU_FRSP_FCONV_GRP80 | FPU executed FRSP or FCONV instructions | 2 | Group 80 pm_fpu2 |
| PM_FPU_FIN_GRP80 | FPU produced a result | 3 | Group 80 pm_fpu2 |
| PM_INST_CMPL_GRP80 | Instructions completed | 4 | Group 80 pm_fpu2 |
| PM_RUN_CYC_GRP80 | Run cycles | 5 | Group 80 pm_fpu2 |
| PM_FPU_DENORM_GRP81 | FPU received denormalized data | 0 | Group 81 pm_fpu3 |
| PM_FPU_STALL3_GRP81 | FPU stalled in pipe3 | 1 | Group 81 pm_fpu3 |
| PM_FPU0_FIN_GRP81 | FPU0 produced a result | 2 | Group 81 pm_fpu3 |
| PM_FPU1_FIN_GRP81 | FPU1 produced a result | 3 | Group 81 pm_fpu3 |
| PM_INST_CMPL_GRP81 | Instructions completed | 4 | Group 81 pm_fpu3 |
| PM_RUN_CYC_GRP81 | Run cycles | 5 | Group 81 pm_fpu3 |
| PM_FPU_SINGLE_GRP82 | FPU executed single precision instruction | 0 | Group 82 pm_fpu4 |
| PM_FPU_STF_GRP82 | FPU executed store instruction | 1 | Group 82 pm_fpu4 |
| PM_IOPS_CMPL_GRP82 | IOPS instructions completed | 2 | Group 82 pm_fpu4 |
| PM_LSU_LDF_GRP82 | LSU executed Floating Point load instruction | 3 | Group 82 pm_fpu4 |
| PM_INST_CMPL_GRP82 | Instructions completed | 4 | Group 82 pm_fpu4 |
| PM_RUN_CYC_GRP82 | Run cycles | 5 | Group 82 pm_fpu4 |
| PM_FPU0_FSQRT_GRP83 | FPU0 executed FSQRT instruction | 0 | Group 83 pm_fpu5 |
| PM_FPU1_FSQRT_GRP83 | FPU1 executed FSQRT instruction | 1 | Group 83 pm_fpu5 |
| PM_FPU0_FEST_GRP83 | FPU0 executed FEST instruction | 2 | Group 83 pm_fpu5 |
| PM_FPU1_FEST_GRP83 | FPU1 executed FEST instruction | 3 | Group 83 pm_fpu5 |
| PM_INST_CMPL_GRP83 | Instructions completed | 4 | Group 83 pm_fpu5 |
| PM_RUN_CYC_GRP83 | Run cycles | 5 | Group 83 pm_fpu5 |
| PM_FPU0_DENORM_GRP84 | FPU0 received denormalized data | 0 | Group 84 pm_fpu6 |
| PM_FPU1_DENORM_GRP84 | FPU1 received denormalized data | 1 | Group 84 pm_fpu6 |
| PM_FPU0_FMOV_FEST_GRP84 | FPU0 executed FMOV or FEST instructions | 2 | Group 84 pm_fpu6 |
| PM_FPU1_FMOV_FEST_GRP84 | FPU1 executing FMOV or FEST instructions | 3 | Group 84 pm_fpu6 |
| PM_INST_CMPL_GRP84 | Instructions completed | 4 | Group 84 pm_fpu6 |
| PM_RUN_CYC_GRP84 | Run cycles | 5 | Group 84 pm_fpu6 |
| PM_FPU0_FDIV_GRP85 | FPU0 executed FDIV instruction | 0 | Group 85 pm_fpu7 |
| PM_FPU1_FDIV_GRP85 | FPU1 executed FDIV instruction | 1 | Group 85 pm_fpu7 |
| PM_FPU0_FRSP_FCONV_GRP85 | FPU0 executed FRSP or FCONV instructions | 2 | Group 85 pm_fpu7 |
| PM_FPU1_FRSP_FCONV_GRP85 | FPU1 executed FRSP or FCONV instructions | 3 | Group 85 pm_fpu7 |
| PM_INST_CMPL_GRP85 | Instructions completed | 4 | Group 85 pm_fpu7 |
| PM_RUN_CYC_GRP85 | Run cycles | 5 | Group 85 pm_fpu7 |
| PM_FPU0_STALL3_GRP86 | FPU0 stalled in pipe3 | 0 | Group 86 pm_fpu8 |
| PM_FPU1_STALL3_GRP86 | FPU1 stalled in pipe3 | 1 | Group 86 pm_fpu8 |
| PM_IOPS_CMPL_GRP86 | IOPS instructions completed | 2 | Group 86 pm_fpu8 |
| PM_FPU0_FPSCR_GRP86 | FPU0 executed FPSCR instruction | 3 | Group 86 pm_fpu8 |
| PM_INST_CMPL_GRP86 | Instructions completed | 4 | Group 86 pm_fpu8 |
| PM_RUN_CYC_GRP86 | Run cycles | 5 | Group 86 pm_fpu8 |
| PM_FPU0_SINGLE_GRP87 | FPU0 executed single precision instruction | 0 | Group 87 pm_fpu9 |
| PM_FPU1_SINGLE_GRP87 | FPU1 executed single precision instruction | 1 | Group 87 pm_fpu9 |
| PM_LSU0_LDF_GRP87 | LSU0 executed Floating Point load instruction | 2 | Group 87 pm_fpu9 |
| PM_LSU1_LDF_GRP87 | LSU1 executed Floating Point load instruction | 3 | Group 87 pm_fpu9 |
| PM_INST_CMPL_GRP87 | Instructions completed | 4 | Group 87 pm_fpu9 |
| PM_RUN_CYC_GRP87 | Run cycles | 5 | Group 87 pm_fpu9 |
| PM_FPU0_FMA_GRP88 | FPU0 executed multiply-add instruction | 0 | Group 88 pm_fpu10 |
| PM_FPU1_FMA_GRP88 | FPU1 executed multiply-add instruction | 1 | Group 88 pm_fpu10 |
| PM_IOPS_CMPL_GRP88 | IOPS instructions completed | 2 | Group 88 pm_fpu10 |
| PM_FPU1_FRSP_FCONV_GRP88 | FPU1 executed FRSP or FCONV instructions | 3 | Group 88 pm_fpu10 |
| PM_INST_CMPL_GRP88 | Instructions completed | 4 | Group 88 pm_fpu10 |
| PM_RUN_CYC_GRP88 | Run cycles | 5 | Group 88 pm_fpu10 |
| PM_FPU0_1FLOP_GRP89 | FPU0 executed add, mult, sub, cmp or sel instruction | 0 | Group 89 pm_fpu11 |
| PM_FPU1_1FLOP_GRP89 | FPU1 executed add, mult, sub, cmp or sel instruction | 1 | Group 89 pm_fpu11 |
| PM_FPU0_FIN_GRP89 | FPU0 produced a result | 2 | Group 89 pm_fpu11 |
| PM_IOPS_CMPL_GRP89 | IOPS instructions completed | 3 | Group 89 pm_fpu11 |
| PM_INST_CMPL_GRP89 | Instructions completed | 4 | Group 89 pm_fpu11 |
| PM_RUN_CYC_GRP89 | Run cycles | 5 | Group 89 pm_fpu11 |
| PM_FPU0_STF_GRP90 | FPU0 executed store instruction | 0 | Group 90 pm_fpu12 |
| PM_FPU1_STF_GRP90 | FPU1 executed store instruction | 1 | Group 90 pm_fpu12 |
| PM_LSU0_LDF_GRP90 | LSU0 executed Floating Point load instruction | 2 | Group 90 pm_fpu12 |
| PM_IOPS_CMPL_GRP90 | IOPS instructions completed | 3 | Group 90 pm_fpu12 |
| PM_INST_CMPL_GRP90 | Instructions completed | 4 | Group 90 pm_fpu12 |
| PM_RUN_CYC_GRP90 | Run cycles | 5 | Group 90 pm_fpu12 |
| PM_FXU_IDLE_GRP91 | FXU idle | 0 | Group 91 pm_fxu1 |
| PM_FXU_BUSY_GRP91 | FXU busy | 1 | Group 91 pm_fxu1 |
| PM_FXU0_BUSY_FXU1_IDLE_GRP91 | FXU0 busy FXU1 idle | 2 | Group 91 pm_fxu1 |
| PM_FXU1_BUSY_FXU0_IDLE_GRP91 | FXU1 busy FXU0 idle | 3 | Group 91 pm_fxu1 |
| PM_INST_CMPL_GRP91 | Instructions completed | 4 | Group 91 pm_fxu1 |
| PM_RUN_CYC_GRP91 | Run cycles | 5 | Group 91 pm_fxu1 |
| PM_MRK_GRP_DISP_GRP92 | Marked group dispatched | 0 | Group 92 pm_fxu2 |
| PM_MRK_GRP_BR_REDIR_GRP92 | Group experienced marked branch redirect | 1 | Group 92 pm_fxu2 |
| PM_FXU_FIN_GRP92 | FXU produced a result | 2 | Group 92 pm_fxu2 |
| PM_FXLS_FULL_CYC_GRP92 | Cycles FXLS queue is full | 3 | Group 92 pm_fxu2 |
| PM_INST_CMPL_GRP92 | Instructions completed | 4 | Group 92 pm_fxu2 |
| PM_RUN_CYC_GRP92 | Run cycles | 5 | Group 92 pm_fxu2 |
| PM_3INST_CLB_CYC_GRP93 | Cycles 3 instructions in CLB | 0 | Group 93 pm_fxu3 |
| PM_4INST_CLB_CYC_GRP93 | Cycles 4 instructions in CLB | 1 | Group 93 pm_fxu3 |
| PM_FXU0_FIN_GRP93 | FXU0 produced a result | 2 | Group 93 pm_fxu3 |
| PM_FXU1_FIN_GRP93 | FXU1 produced a result | 3 | Group 93 pm_fxu3 |
| PM_INST_CMPL_GRP93 | Instructions completed | 4 | Group 93 pm_fxu3 |
| PM_RUN_CYC_GRP93 | Run cycles | 5 | Group 93 pm_fxu3 |
| PM_THRD_PRIO_4_CYC_GRP94 | Cycles thread running at priority level 4 | 0 | Group 94 pm_smt_priorities1 |
| PM_THRD_PRIO_7_CYC_GRP94 | Cycles thread running at priority level 7 | 1 | Group 94 pm_smt_priorities1 |
| PM_THRD_PRIO_DIFF_0_CYC_GRP94 | Cycles no thread priority difference | 2 | Group 94 pm_smt_priorities1 |
| PM_THRD_PRIO_DIFF_1or2_CYC_GRP94 | Cycles thread priority difference is 1 or 2 | 3 | Group 94 pm_smt_priorities1 |
| PM_INST_CMPL_GRP94 | Instructions completed | 4 | Group 94 pm_smt_priorities1 |
| PM_RUN_CYC_GRP94 | Run cycles | 5 | Group 94 pm_smt_priorities1 |
| PM_THRD_PRIO_3_CYC_GRP95 | Cycles thread running at priority level 3 | 0 | Group 95 pm_smt_priorities2 |
| PM_THRD_PRIO_6_CYC_GRP95 | Cycles thread running at priority level 6 | 1 | Group 95 pm_smt_priorities2 |
| PM_THRD_PRIO_DIFF_3or4_CYC_GRP95 | Cycles thread priority difference is 3 or 4 | 2 | Group 95 pm_smt_priorities2 |
| PM_THRD_PRIO_DIFF_5or6_CYC_GRP95 | Cycles thread priority difference is 5 or 6 | 3 | Group 95 pm_smt_priorities2 |
| PM_INST_CMPL_GRP95 | Instructions completed | 4 | Group 95 pm_smt_priorities2 |
| PM_RUN_CYC_GRP95 | Run cycles | 5 | Group 95 pm_smt_priorities2 |
| PM_THRD_PRIO_2_CYC_GRP96 | Cycles thread running at priority level 2 | 0 | Group 96 pm_smt_priorities3 |
| PM_THRD_PRIO_5_CYC_GRP96 | Cycles thread running at priority level 5 | 1 | Group 96 pm_smt_priorities3 |
| PM_THRD_PRIO_DIFF_minus1or2_CYC_GRP96 | Cycles thread priority difference is -1 or -2 | 2 | Group 96 pm_smt_priorities3 |
| PM_THRD_PRIO_DIFF_minus3or4_CYC_GRP96 | Cycles thread priority difference is -3 or -4 | 3 | Group 96 pm_smt_priorities3 |
| PM_INST_CMPL_GRP96 | Instructions completed | 4 | Group 96 pm_smt_priorities3 |
| PM_RUN_CYC_GRP96 | Run cycles | 5 | Group 96 pm_smt_priorities3 |
| PM_THRD_PRIO_1_CYC_GRP97 | Cycles thread running at priority level 1 | 0 | Group 97 pm_smt_priorities4 |
| PM_HV_CYC_GRP97 | Hypervisor Cycles | 1 | Group 97 pm_smt_priorities4 |
| PM_THRD_PRIO_DIFF_minus5or6_CYC_GRP97 | Cycles thread priority difference is -5 or -6 | 2 | Group 97 pm_smt_priorities4 |
| PM_IOPS_CMPL_GRP97 | IOPS instructions completed | 3 | Group 97 pm_smt_priorities4 |
| PM_INST_CMPL_GRP97 | Instructions completed | 4 | Group 97 pm_smt_priorities4 |
| PM_RUN_CYC_GRP97 | Run cycles | 5 | Group 97 pm_smt_priorities4 |
| PM_THRD_ONE_RUN_CYC_GRP98 | One of the threads in run cycles | 0 | Group 98 pm_smt_both |
| PM_THRD_GRP_CMPL_BOTH_CYC_GRP98 | Cycles group completed by both threads | 1 | Group 98 pm_smt_both |
| PM_IOPS_CMPL_GRP98 | IOPS instructions completed | 2 | Group 98 pm_smt_both |
| PM_THRD_L2MISS_BOTH_CYC_GRP98 | Cycles both threads in L2 misses | 3 | Group 98 pm_smt_both |
| PM_INST_CMPL_GRP98 | Instructions completed | 4 | Group 98 pm_smt_both |
| PM_RUN_CYC_GRP98 | Run cycles | 5 | Group 98 pm_smt_both |
| PM_SNOOP_TLBIE_GRP99 | Snoop TLBIE | 0 | Group 99 pm_smt_selection |
| PM_IOPS_CMPL_GRP99 | IOPS instructions completed | 1 | Group 99 pm_smt_selection |
| PM_THRD_SEL_T0_GRP99 | Decode selected thread 0 | 2 | Group 99 pm_smt_selection |
| PM_THRD_SEL_T1_GRP99 | Decode selected thread 1 | 3 | Group 99 pm_smt_selection |
| PM_INST_CMPL_GRP99 | Instructions completed | 4 | Group 99 pm_smt_selection |
| PM_RUN_CYC_GRP99 | Run cycles | 5 | Group 99 pm_smt_selection |
| PM_IOPS_CMPL_GRP100 | IOPS instructions completed | 0 | Group 100 pm_smt_selectover1 |
| PM_0INST_CLB_CYC_GRP100 | Cycles no instructions in CLB | 1 | Group 100 pm_smt_selectover1 |
| PM_THRD_SEL_OVER_CLB_EMPTY_GRP100 | Thread selection overides caused by CLB empty | 2 | Group 100 pm_smt_selectover1 |
| PM_THRD_SEL_OVER_GCT_IMBAL_GRP100 | Thread selection overides caused by GCT imbalance | 3 | Group 100 pm_smt_selectover1 |
| PM_INST_CMPL_GRP100 | Instructions completed | 4 | Group 100 pm_smt_selectover1 |
| PM_RUN_CYC_GRP100 | Run cycles | 5 | Group 100 pm_smt_selectover1 |
| PM_IOPS_CMPL_GRP101 | IOPS instructions completed | 0 | Group 101 pm_smt_selectover2 |
| PM_CYC_GRP101 | Processor cycles | 1 | Group 101 pm_smt_selectover2 |
| PM_THRD_SEL_OVER_ISU_HOLD_GRP101 | Thread selection overides caused by ISU holds | 2 | Group 101 pm_smt_selectover2 |
| PM_THRD_SEL_OVER_L2MISS_GRP101 | Thread selection overides caused by L2 misses | 3 | Group 101 pm_smt_selectover2 |
| PM_INST_CMPL_GRP101 | Instructions completed | 4 | Group 101 pm_smt_selectover2 |
| PM_RUN_CYC_GRP101 | Run cycles | 5 | Group 101 pm_smt_selectover2 |
| PM_FAB_CMD_ISSUED_GRP102 | Fabric command issued | 0 | Group 102 pm_fabric1 |
| PM_FAB_DCLAIM_ISSUED_GRP102 | dclaim issued | 1 | Group 102 pm_fabric1 |
| PM_FAB_CMD_RETRIED_GRP102 | Fabric command retried | 2 | Group 102 pm_fabric1 |
| PM_FAB_DCLAIM_RETRIED_GRP102 | dclaim retried | 3 | Group 102 pm_fabric1 |
| PM_INST_CMPL_GRP102 | Instructions completed | 4 | Group 102 pm_fabric1 |
| PM_RUN_CYC_GRP102 | Run cycles | 5 | Group 102 pm_fabric1 |
| PM_FAB_P1toM1_SIDECAR_EMPTY_GRP103 | P1 to M1 sidecar empty | 0 | Group 103 pm_fabric2 |
| PM_FAB_HOLDtoVN_EMPTY_GRP103 | Hold buffer to VN empty | 1 | Group 103 pm_fabric2 |
| PM_FAB_P1toVNorNN_SIDECAR_EMPTY_GRP103 | P1 to VN/NN sidecar empty | 2 | Group 103 pm_fabric2 |
| PM_FAB_VBYPASS_EMPTY_GRP103 | Vertical bypass buffer empty | 3 | Group 103 pm_fabric2 |
| PM_INST_CMPL_GRP103 | Instructions completed | 4 | Group 103 pm_fabric2 |
| PM_RUN_CYC_GRP103 | Run cycles | 5 | Group 103 pm_fabric2 |
| PM_FAB_PNtoNN_DIRECT_GRP104 | PN to NN beat went straight to its destination | 0 | Group 104 pm_fabric3 |
| PM_FAB_PNtoVN_DIRECT_GRP104 | PN to VN beat went straight to its destination | 1 | Group 104 pm_fabric3 |
| PM_FAB_PNtoNN_SIDECAR_GRP104 | PN to NN beat went to sidecar first | 2 | Group 104 pm_fabric3 |
| PM_FAB_PNtoVN_SIDECAR_GRP104 | PN to VN beat went to sidecar first | 3 | Group 104 pm_fabric3 |
| PM_INST_CMPL_GRP104 | Instructions completed | 4 | Group 104 pm_fabric3 |
| PM_RUN_CYC_GRP104 | Run cycles | 5 | Group 104 pm_fabric3 |
| PM_FAB_M1toP1_SIDECAR_EMPTY_GRP105 | M1 to P1 sidecar empty | 0 | Group 105 pm_fabric4 |
| PM_FAB_HOLDtoNN_EMPTY_GRP105 | Hold buffer to NN empty | 1 | Group 105 pm_fabric4 |
| PM_EE_OFF_GRP105 | Cycles MSR(EE) bit off | 2 | Group 105 pm_fabric4 |
| PM_FAB_M1toVNorNN_SIDECAR_EMPTY_GRP105 | M1 to VN/NN sidecar empty | 3 | Group 105 pm_fabric4 |
| PM_INST_CMPL_GRP105 | Instructions completed | 4 | Group 105 pm_fabric4 |
| PM_RUN_CYC_GRP105 | Run cycles | 5 | Group 105 pm_fabric4 |
| PM_SNOOP_RD_RETRY_QFULL_GRP106 | Snoop read retry due to read queue full | 0 | Group 106 pm_snoop1 |
| PM_SNOOP_DCLAIM_RETRY_QFULL_GRP106 | Snoop dclaim/flush retry due to write/dclaim queues full | 1 | Group 106 pm_snoop1 |
| PM_SNOOP_WR_RETRY_QFULL_GRP106 | Snoop read retry due to read queue full | 2 | Group 106 pm_snoop1 |
| PM_SNOOP_PARTIAL_RTRY_QFULL_GRP106 | Snoop partial write retry due to partial-write queues full | 3 | Group 106 pm_snoop1 |
| PM_INST_CMPL_GRP106 | Instructions completed | 4 | Group 106 pm_snoop1 |
| PM_RUN_CYC_GRP106 | Run cycles | 5 | Group 106 pm_snoop1 |
| PM_SNOOP_RD_RETRY_RQ_GRP107 | Snoop read retry due to collision with active read queue | 0 | Group 107 pm_snoop2 |
| PM_SNOOP_RETRY_1AHEAD_GRP107 | Snoop retry due to one ahead collision | 1 | Group 107 pm_snoop2 |
| PM_SNOOP_RD_RETRY_WQ_GRP107 | Snoop read retry due to collision with active write queue | 2 | Group 107 pm_snoop2 |
| PM_IOPS_CMPL_GRP107 | IOPS instructions completed | 3 | Group 107 pm_snoop2 |
| PM_INST_CMPL_GRP107 | Instructions completed | 4 | Group 107 pm_snoop2 |
| PM_RUN_CYC_GRP107 | Run cycles | 5 | Group 107 pm_snoop2 |
| PM_SNOOP_WR_RETRY_RQ_GRP108 | Snoop write/dclaim retry due to collision with active read queue | 0 | Group 108 pm_snoop3 |
| PM_MEM_HI_PRIO_WR_CMPL_GRP108 | High priority write completed | 1 | Group 108 pm_snoop3 |
| PM_SNOOP_WR_RETRY_WQ_GRP108 | Snoop write/dclaim retry due to collision with active write queue | 2 | Group 108 pm_snoop3 |
| PM_MEM_LO_PRIO_WR_CMPL_GRP108 | Low priority write completed | 3 | Group 108 pm_snoop3 |
| PM_INST_CMPL_GRP108 | Instructions completed | 4 | Group 108 pm_snoop3 |
| PM_RUN_CYC_GRP108 | Run cycles | 5 | Group 108 pm_snoop3 |
| PM_SNOOP_PW_RETRY_RQ_GRP109 | Snoop partial-write retry due to collision with active read queue | 0 | Group 109 pm_snoop4 |
| PM_MEM_HI_PRIO_PW_CMPL_GRP109 | High priority partial-write completed | 1 | Group 109 pm_snoop4 |
| PM_SNOOP_PW_RETRY_WQ_PWQ_GRP109 | Snoop partial-write retry due to collision with active write or partial-write queue | 2 | Group 109 pm_snoop4 |
| PM_MEM_LO_PRIO_PW_CMPL_GRP109 | Low priority partial-write completed | 3 | Group 109 pm_snoop4 |
| PM_INST_CMPL_GRP109 | Instructions completed | 4 | Group 109 pm_snoop4 |
| PM_RUN_CYC_GRP109 | Run cycles | 5 | Group 109 pm_snoop4 |
| PM_MEM_RQ_DISP_GRP110 | Memory read queue dispatched | 0 | Group 110 pm_mem_rq |
| PM_MEM_RQ_DISP_BUSY8to15_GRP110 | Memory read queue dispatched with 8-15 queues busy | 1 | Group 110 pm_mem_rq |
| PM_MEM_RQ_DISP_BUSY1to7_GRP110 | Memory read queue dispatched with 1-7 queues busy | 2 | Group 110 pm_mem_rq |
| PM_EE_OFF_EXT_INT_GRP110 | Cycles MSR(EE) bit off and external interrupt pending | 3 | Group 110 pm_mem_rq |
| PM_INST_CMPL_GRP110 | Instructions completed | 4 | Group 110 pm_mem_rq |
| PM_RUN_CYC_GRP110 | Run cycles | 5 | Group 110 pm_mem_rq |
| PM_MEM_READ_CMPL_GRP111 | Memory read completed or canceled | 0 | Group 111 pm_mem_read |
| PM_MEM_FAST_PATH_RD_CMPL_GRP111 | Fast path memory read completed | 1 | Group 111 pm_mem_read |
| PM_MEM_SPEC_RD_CANCEL_GRP111 | Speculative memory read canceled | 2 | Group 111 pm_mem_read |
| PM_EXT_INT_GRP111 | External interrupts | 3 | Group 111 pm_mem_read |
| PM_INST_CMPL_GRP111 | Instructions completed | 4 | Group 111 pm_mem_read |
| PM_RUN_CYC_GRP111 | Run cycles | 5 | Group 111 pm_mem_read |
| PM_MEM_WQ_DISP_WRITE_GRP112 | Memory write queue dispatched due to write | 0 | Group 112 pm_mem_wq |
| PM_MEM_WQ_DISP_BUSY1to7_GRP112 | Memory write queue dispatched with 1-7 queues busy | 1 | Group 112 pm_mem_wq |
| PM_MEM_WQ_DISP_DCLAIM_GRP112 | Memory write queue dispatched due to dclaim/flush | 2 | Group 112 pm_mem_wq |
| PM_MEM_WQ_DISP_BUSY8to15_GRP112 | Memory write queue dispatched with 8-15 queues busy | 3 | Group 112 pm_mem_wq |
| PM_INST_CMPL_GRP112 | Instructions completed | 4 | Group 112 pm_mem_wq |
| PM_RUN_CYC_GRP112 | Run cycles | 5 | Group 112 pm_mem_wq |
| PM_MEM_PWQ_DISP_GRP113 | Memory partial-write queue dispatched | 0 | Group 113 pm_mem_pwq |
| PM_MEM_PWQ_DISP_BUSY2or3_GRP113 | Memory partial-write queue dispatched with 2-3 queues busy | 1 | Group 113 pm_mem_pwq |
| PM_MEM_PW_GATH_GRP113 | Memory partial-write gathered | 2 | Group 113 pm_mem_pwq |
| PM_MEM_PW_CMPL_GRP113 | Memory partial-write completed | 3 | Group 113 pm_mem_pwq |
| PM_INST_CMPL_GRP113 | Instructions completed | 4 | Group 113 pm_mem_pwq |
| PM_RUN_CYC_GRP113 | Run cycles | 5 | Group 113 pm_mem_pwq |
| PM_MRK_GRP_DISP_GRP114 | Marked group dispatched | 0 | Group 114 pm_threshold |
| PM_MRK_IMR_RELOAD_GRP114 | Marked IMR reloaded | 1 | Group 114 pm_threshold |
| PM_THRESH_TIMEO_GRP114 | Threshold timeout | 2 | Group 114 pm_threshold |
| PM_MRK_LSU_FIN_GRP114 | Marked instruction LSU processing finished | 3 | Group 114 pm_threshold |
| PM_INST_CMPL_GRP114 | Instructions completed | 4 | Group 114 pm_threshold |
| PM_RUN_CYC_GRP114 | Run cycles | 5 | Group 114 pm_threshold |
| PM_MRK_GRP_DISP_GRP115 | Marked group dispatched | 0 | Group 115 pm_mrk_grp1 |
| PM_MRK_ST_MISS_L1_GRP115 | Marked L1 D cache store misses | 1 | Group 115 pm_mrk_grp1 |
| PM_MRK_INST_FIN_GRP115 | Marked instruction finished | 2 | Group 115 pm_mrk_grp1 |
| PM_MRK_GRP_CMPL_GRP115 | Marked group completed | 3 | Group 115 pm_mrk_grp1 |
| PM_INST_CMPL_GRP115 | Instructions completed | 4 | Group 115 pm_mrk_grp1 |
| PM_RUN_CYC_GRP115 | Run cycles | 5 | Group 115 pm_mrk_grp1 |
| PM_MRK_GRP_ISSUED_GRP116 | Marked group issued | 0 | Group 116 pm_mrk_grp2 |
| PM_MRK_BRU_FIN_GRP116 | Marked instruction BRU processing finished | 1 | Group 116 pm_mrk_grp2 |
| PM_MRK_L1_RELOAD_VALID_GRP116 | Marked L1 reload data source valid | 2 | Group 116 pm_mrk_grp2 |
| PM_MRK_GRP_IC_MISS_GRP116 | Group experienced marked I cache miss | 3 | Group 116 pm_mrk_grp2 |
| PM_INST_CMPL_GRP116 | Instructions completed | 4 | Group 116 pm_mrk_grp2 |
| PM_RUN_CYC_GRP116 | Run cycles | 5 | Group 116 pm_mrk_grp2 |
| PM_MRK_DATA_FROM_L2_GRP117 | Marked data loaded from L2 | 0 | Group 117 pm_mrk_dsource1 |
| PM_MRK_DATA_FROM_L2_CYC_GRP117 | Marked load latency from L2 | 1 | Group 117 pm_mrk_dsource1 |
| PM_MRK_DATA_FROM_L25_MOD_GRP117 | Marked data loaded from L2.5 modified | 2 | Group 117 pm_mrk_dsource1 |
| PM_MRK_DATA_FROM_L25_MOD_CYC_GRP117 | Marked load latency from L2.5 modified | 3 | Group 117 pm_mrk_dsource1 |
| PM_INST_CMPL_GRP117 | Instructions completed | 4 | Group 117 pm_mrk_dsource1 |
| PM_RUN_CYC_GRP117 | Run cycles | 5 | Group 117 pm_mrk_dsource1 |
| PM_MRK_DATA_FROM_L25_SHR_GRP118 | Marked data loaded from L2.5 shared | 0 | Group 118 pm_mrk_dsource2 |
| PM_MRK_DATA_FROM_L25_SHR_CYC_GRP118 | Marked load latency from L2.5 shared | 1 | Group 118 pm_mrk_dsource2 |
| PM_IOPS_CMPL_GRP118 | IOPS instructions completed | 2 | Group 118 pm_mrk_dsource2 |
| PM_FPU_FIN_GRP118 | FPU produced a result | 3 | Group 118 pm_mrk_dsource2 |
| PM_INST_CMPL_GRP118 | Instructions completed | 4 | Group 118 pm_mrk_dsource2 |
| PM_RUN_CYC_GRP118 | Run cycles | 5 | Group 118 pm_mrk_dsource2 |
| PM_MRK_DATA_FROM_L3_GRP119 | Marked data loaded from L3 | 0 | Group 119 pm_mrk_dsource3 |
| PM_MRK_DATA_FROM_L3_CYC_GRP119 | Marked load latency from L3 | 1 | Group 119 pm_mrk_dsource3 |
| PM_MRK_DATA_FROM_L35_MOD_GRP119 | Marked data loaded from L3.5 modified | 2 | Group 119 pm_mrk_dsource3 |
| PM_MRK_DATA_FROM_L35_MOD_CYC_GRP119 | Marked load latency from L3.5 modified | 3 | Group 119 pm_mrk_dsource3 |
| PM_INST_CMPL_GRP119 | Instructions completed | 4 | Group 119 pm_mrk_dsource3 |
| PM_RUN_CYC_GRP119 | Run cycles | 5 | Group 119 pm_mrk_dsource3 |
| PM_MRK_DATA_FROM_RMEM_GRP120 | Marked data loaded from remote memory | 0 | Group 120 pm_mrk_dsource4 |
| PM_MRK_DATA_FROM_L275_SHR_CYC_GRP120 | Marked load latency from L2.75 shared | 1 | Group 120 pm_mrk_dsource4 |
| PM_MRK_DATA_FROM_L275_SHR_GRP120 | Marked data loaded from L2.75 shared | 2 | Group 120 pm_mrk_dsource4 |
| PM_MRK_DATA_FROM_RMEM_CYC_GRP120 | Marked load latency from remote memory | 3 | Group 120 pm_mrk_dsource4 |
| PM_INST_CMPL_GRP120 | Instructions completed | 4 | Group 120 pm_mrk_dsource4 |
| PM_RUN_CYC_GRP120 | Run cycles | 5 | Group 120 pm_mrk_dsource4 |
| PM_MRK_DATA_FROM_L35_SHR_GRP121 | Marked data loaded from L3.5 shared | 0 | Group 121 pm_mrk_dsource5 |
| PM_MRK_DATA_FROM_L35_SHR_CYC_GRP121 | Marked load latency from L3.5 shared | 1 | Group 121 pm_mrk_dsource5 |
| PM_MRK_DATA_FROM_LMEM_GRP121 | Marked data loaded from local memory | 2 | Group 121 pm_mrk_dsource5 |
| PM_MRK_DATA_FROM_LMEM_CYC_GRP121 | Marked load latency from local memory | 3 | Group 121 pm_mrk_dsource5 |
| PM_INST_CMPL_GRP121 | Instructions completed | 4 | Group 121 pm_mrk_dsource5 |
| PM_RUN_CYC_GRP121 | Run cycles | 5 | Group 121 pm_mrk_dsource5 |
| PM_MRK_DATA_FROM_L275_MOD_GRP122 | Marked data loaded from L2.75 modified | 0 | Group 122 pm_mrk_dsource6 |
| PM_MRK_DATA_FROM_L275_SHR_CYC_GRP122 | Marked load latency from L2.75 shared | 1 | Group 122 pm_mrk_dsource6 |
| PM_IOPS_CMPL_GRP122 | IOPS instructions completed | 2 | Group 122 pm_mrk_dsource6 |
| PM_MRK_DATA_FROM_L275_MOD_CYC_GRP122 | Marked load latency from L2.75 modified | 3 | Group 122 pm_mrk_dsource6 |
| PM_INST_CMPL_GRP122 | Instructions completed | 4 | Group 122 pm_mrk_dsource6 |
| PM_RUN_CYC_GRP122 | Run cycles | 5 | Group 122 pm_mrk_dsource6 |
| PM_MRK_DATA_FROM_L375_MOD_GRP123 | Marked data loaded from L3.75 modified | 0 | Group 123 pm_mrk_dsource7 |
| PM_MRK_DATA_FROM_L375_SHR_CYC_GRP123 | Marked load latency from L3.75 shared | 1 | Group 123 pm_mrk_dsource7 |
| PM_MRK_DATA_FROM_L375_SHR_GRP123 | Marked data loaded from L3.75 shared | 2 | Group 123 pm_mrk_dsource7 |
| PM_MRK_DATA_FROM_L375_MOD_CYC_GRP123 | Marked load latency from L3.75 modified | 3 | Group 123 pm_mrk_dsource7 |
| PM_INST_CMPL_GRP123 | Instructions completed | 4 | Group 123 pm_mrk_dsource7 |
| PM_RUN_CYC_GRP123 | Run cycles | 5 | Group 123 pm_mrk_dsource7 |
| PM_MRK_DTLB_MISS_4K_GRP124 | Marked Data TLB misses for 4K page | 0 | Group 124 pm_mrk_lbmiss |
| PM_MRK_DTLB_MISS_16M_GRP124 | Marked Data TLB misses for 16M page | 1 | Group 124 pm_mrk_lbmiss |
| PM_MRK_DTLB_MISS_GRP124 | Marked Data TLB misses | 2 | Group 124 pm_mrk_lbmiss |
| PM_MRK_DSLB_MISS_GRP124 | Marked Data SLB misses | 3 | Group 124 pm_mrk_lbmiss |
| PM_INST_CMPL_GRP124 | Instructions completed | 4 | Group 124 pm_mrk_lbmiss |
| PM_RUN_CYC_GRP124 | Run cycles | 5 | Group 124 pm_mrk_lbmiss |
| PM_MRK_DTLB_REF_4K_GRP125 | Marked Data TLB reference for 4K page | 0 | Group 125 pm_mrk_lbref |
| PM_MRK_DTLB_REF_16M_GRP125 | Marked Data TLB reference for 16M page | 1 | Group 125 pm_mrk_lbref |
| PM_IOPS_CMPL_GRP125 | IOPS instructions completed | 2 | Group 125 pm_mrk_lbref |
| PM_MRK_DSLB_MISS_GRP125 | Marked Data SLB misses | 3 | Group 125 pm_mrk_lbref |
| PM_INST_CMPL_GRP125 | Instructions completed | 4 | Group 125 pm_mrk_lbref |
| PM_RUN_CYC_GRP125 | Run cycles | 5 | Group 125 pm_mrk_lbref |
| PM_MRK_LD_MISS_L1_GRP126 | Marked L1 D cache load misses | 0 | Group 126 pm_mrk_lsmiss |
| PM_IOPS_CMPL_GRP126 | IOPS instructions completed | 1 | Group 126 pm_mrk_lsmiss |
| PM_MRK_ST_CMPL_INT_GRP126 | Marked store completed with intervention | 2 | Group 126 pm_mrk_lsmiss |
| PM_MRK_CRU_FIN_GRP126 | Marked instruction CRU processing finished | 3 | Group 126 pm_mrk_lsmiss |
| PM_INST_CMPL_GRP126 | Instructions completed | 4 | Group 126 pm_mrk_lsmiss |
| PM_RUN_CYC_GRP126 | Run cycles | 5 | Group 126 pm_mrk_lsmiss |
| PM_MRK_ST_CMPL_GRP127 | Marked store instruction completed | 0 | Group 127 pm_mrk_ulsflush |
| PM_MRK_ST_MISS_L1_GRP127 | Marked L1 D cache store misses | 1 | Group 127 pm_mrk_ulsflush |
| PM_MRK_LSU_FLUSH_UST_GRP127 | Marked unaligned store flushes | 2 | Group 127 pm_mrk_ulsflush |
| PM_MRK_LSU_FLUSH_ULD_GRP127 | Marked unaligned load flushes | 3 | Group 127 pm_mrk_ulsflush |
| PM_INST_CMPL_GRP127 | Instructions completed | 4 | Group 127 pm_mrk_ulsflush |
| PM_RUN_CYC_GRP127 | Run cycles | 5 | Group 127 pm_mrk_ulsflush |
| PM_MRK_STCX_FAIL_GRP128 | Marked STCX failed | 0 | Group 128 pm_mrk_misc |
| PM_MRK_ST_GPS_GRP128 | Marked store sent to GPS | 1 | Group 128 pm_mrk_misc |
| PM_MRK_FPU_FIN_GRP128 | Marked instruction FPU processing finished | 2 | Group 128 pm_mrk_misc |
| PM_MRK_GRP_TIMEO_GRP128 | Marked group completion timeout | 3 | Group 128 pm_mrk_misc |
| PM_INST_CMPL_GRP128 | Instructions completed | 4 | Group 128 pm_mrk_misc |
| PM_RUN_CYC_GRP128 | Run cycles | 5 | Group 128 pm_mrk_misc |
| PM_DATA_FROM_L2_GRP129 | Data loaded from L2 | 0 | Group 129 pm_lsref_L1 |
| PM_INST_FROM_L1_GRP129 | Instruction fetched from L1 | 1 | Group 129 pm_lsref_L1 |
| PM_ST_REF_L1_GRP129 | L1 D cache store references | 2 | Group 129 pm_lsref_L1 |
| PM_LD_REF_L1_GRP129 | L1 D cache load references | 3 | Group 129 pm_lsref_L1 |
| PM_INST_CMPL_GRP129 | Instructions completed | 4 | Group 129 pm_lsref_L1 |
| PM_RUN_CYC_GRP129 | Run cycles | 5 | Group 129 pm_lsref_L1 |
| PM_DATA_FROM_L3_GRP130 | Data loaded from L3 | 0 | Group 130 pm_lsref_L2L3 |
| PM_DATA_FROM_LMEM_GRP130 | Data loaded from local memory | 1 | Group 130 pm_lsref_L2L3 |
| PM_ST_REF_L1_GRP130 | L1 D cache store references | 2 | Group 130 pm_lsref_L2L3 |
| PM_LD_REF_L1_GRP130 | L1 D cache load references | 3 | Group 130 pm_lsref_L2L3 |
| PM_INST_CMPL_GRP130 | Instructions completed | 4 | Group 130 pm_lsref_L2L3 |
| PM_RUN_CYC_GRP130 | Run cycles | 5 | Group 130 pm_lsref_L2L3 |
| PM_ITLB_MISS_GRP131 | Instruction TLB misses | 0 | Group 131 pm_lsref_tlbmiss |
| PM_DTLB_MISS_GRP131 | Data TLB misses | 1 | Group 131 pm_lsref_tlbmiss |
| PM_ST_REF_L1_GRP131 | L1 D cache store references | 2 | Group 131 pm_lsref_tlbmiss |
| PM_LD_REF_L1_GRP131 | L1 D cache load references | 3 | Group 131 pm_lsref_tlbmiss |
| PM_INST_CMPL_GRP131 | Instructions completed | 4 | Group 131 pm_lsref_tlbmiss |
| PM_RUN_CYC_GRP131 | Run cycles | 5 | Group 131 pm_lsref_tlbmiss |
| PM_DATA_FROM_L3_GRP132 | Data loaded from L3 | 0 | Group 132 pm_Dmiss |
| PM_DATA_FROM_LMEM_GRP132 | Data loaded from local memory | 1 | Group 132 pm_Dmiss |
| PM_LD_MISS_L1_GRP132 | L1 D cache load misses | 2 | Group 132 pm_Dmiss |
| PM_ST_MISS_L1_GRP132 | L1 D cache store misses | 3 | Group 132 pm_Dmiss |
| PM_INST_CMPL_GRP132 | Instructions completed | 4 | Group 132 pm_Dmiss |
| PM_RUN_CYC_GRP132 | Run cycles | 5 | Group 132 pm_Dmiss |
| PM_CYC_GRP133 | Processor cycles | 0 | Group 133 pm_prefetchX |
| PM_IC_PREF_REQ_GRP133 | Instruction prefetch requests | 1 | Group 133 pm_prefetchX |
| PM_L1_PREF_GRP133 | L1 cache data prefetches | 2 | Group 133 pm_prefetchX |
| PM_L2_PREF_GRP133 | L2 cache prefetches | 3 | Group 133 pm_prefetchX |
| PM_INST_CMPL_GRP133 | Instructions completed | 4 | Group 133 pm_prefetchX |
| PM_RUN_CYC_GRP133 | Run cycles | 5 | Group 133 pm_prefetchX |
| PM_BR_UNCOND_GRP134 | Unconditional branch | 0 | Group 134 pm_branchX |
| PM_BR_PRED_TA_GRP134 | A conditional branch was predicted, target prediction | 1 | Group 134 pm_branchX |
| PM_BR_PRED_CR_GRP134 | A conditional branch was predicted, CR prediction | 2 | Group 134 pm_branchX |
| PM_BR_ISSUED_GRP134 | Branches issued | 3 | Group 134 pm_branchX |
| PM_INST_CMPL_GRP134 | Instructions completed | 4 | Group 134 pm_branchX |
| PM_RUN_CYC_GRP134 | Run cycles | 5 | Group 134 pm_branchX |
| PM_FPU0_STALL3_GRP135 | FPU0 stalled in pipe3 | 0 | Group 135 pm_fpuX1 |
| PM_FPU1_STALL3_GRP135 | FPU1 stalled in pipe3 | 1 | Group 135 pm_fpuX1 |
| PM_FPU0_FIN_GRP135 | FPU0 produced a result | 2 | Group 135 pm_fpuX1 |
| PM_FPU0_FPSCR_GRP135 | FPU0 executed FPSCR instruction | 3 | Group 135 pm_fpuX1 |
| PM_INST_CMPL_GRP135 | Instructions completed | 4 | Group 135 pm_fpuX1 |
| PM_RUN_CYC_GRP135 | Run cycles | 5 | Group 135 pm_fpuX1 |
| PM_FPU0_FMA_GRP136 | FPU0 executed multiply-add instruction | 0 | Group 136 pm_fpuX2 |
| PM_FPU1_FMA_GRP136 | FPU1 executed multiply-add instruction | 1 | Group 136 pm_fpuX2 |
| PM_FPU0_FRSP_FCONV_GRP136 | FPU0 executed FRSP or FCONV instructions | 2 | Group 136 pm_fpuX2 |
| PM_FPU1_FRSP_FCONV_GRP136 | FPU1 executed FRSP or FCONV instructions | 3 | Group 136 pm_fpuX2 |
| PM_INST_CMPL_GRP136 | Instructions completed | 4 | Group 136 pm_fpuX2 |
| PM_RUN_CYC_GRP136 | Run cycles | 5 | Group 136 pm_fpuX2 |
| PM_FPU0_1FLOP_GRP137 | FPU0 executed add, mult, sub, cmp or sel instruction | 0 | Group 137 pm_fpuX3 |
| PM_FPU1_1FLOP_GRP137 | FPU1 executed add, mult, sub, cmp or sel instruction | 1 | Group 137 pm_fpuX3 |
| PM_FPU0_FIN_GRP137 | FPU0 produced a result | 2 | Group 137 pm_fpuX3 |
| PM_FPU1_FIN_GRP137 | FPU1 produced a result | 3 | Group 137 pm_fpuX3 |
| PM_INST_CMPL_GRP137 | Instructions completed | 4 | Group 137 pm_fpuX3 |
| PM_RUN_CYC_GRP137 | Run cycles | 5 | Group 137 pm_fpuX3 |
| PM_FPU_1FLOP_GRP138 | FPU executed one flop instruction | 0 | Group 138 pm_fpuX4 |
| PM_FPU_FMA_GRP138 | FPU executed multiply-add instruction | 1 | Group 138 pm_fpuX4 |
| PM_ST_REF_L1_GRP138 | L1 D cache store references | 2 | Group 138 pm_fpuX4 |
| PM_LD_REF_L1_GRP138 | L1 D cache load references | 3 | Group 138 pm_fpuX4 |
| PM_INST_CMPL_GRP138 | Instructions completed | 4 | Group 138 pm_fpuX4 |
| PM_RUN_CYC_GRP138 | Run cycles | 5 | Group 138 pm_fpuX4 |
| PM_FPU_SINGLE_GRP139 | FPU executed single precision instruction | 0 | Group 139 pm_fpuX5 |
| PM_FPU_STF_GRP139 | FPU executed store instruction | 1 | Group 139 pm_fpuX5 |
| PM_FPU0_FIN_GRP139 | FPU0 produced a result | 2 | Group 139 pm_fpuX5 |
| PM_FPU1_FIN_GRP139 | FPU1 produced a result | 3 | Group 139 pm_fpuX5 |
| PM_INST_CMPL_GRP139 | Instructions completed | 4 | Group 139 pm_fpuX5 |
| PM_RUN_CYC_GRP139 | Run cycles | 5 | Group 139 pm_fpuX5 |
| PM_FPU_FDIV_GRP140 | FPU executed FDIV instruction | 0 | Group 140 pm_fpuX6 |
| PM_FPU_FSQRT_GRP140 | FPU executed FSQRT instruction | 1 | Group 140 pm_fpuX6 |
| PM_FPU_FRSP_FCONV_GRP140 | FPU executed FRSP or FCONV instructions | 2 | Group 140 pm_fpuX6 |
| PM_FPU_FIN_GRP140 | FPU produced a result | 3 | Group 140 pm_fpuX6 |
| PM_INST_CMPL_GRP140 | Instructions completed | 4 | Group 140 pm_fpuX6 |
| PM_RUN_CYC_GRP140 | Run cycles | 5 | Group 140 pm_fpuX6 |
| PM_FPU_1FLOP_GRP141 | FPU executed one flop instruction | 0 | Group 141 pm_hpmcount1 |
| PM_CYC_GRP141 | Processor cycles | 1 | Group 141 pm_hpmcount1 |
| PM_MRK_FPU_FIN_GRP141 | Marked instruction FPU processing finished | 2 | Group 141 pm_hpmcount1 |
| PM_FPU_FIN_GRP141 | FPU produced a result | 3 | Group 141 pm_hpmcount1 |
| PM_INST_CMPL_GRP141 | Instructions completed | 4 | Group 141 pm_hpmcount1 |
| PM_RUN_CYC_GRP141 | Run cycles | 5 | Group 141 pm_hpmcount1 |
| PM_CYC_GRP142 | Processor cycles | 0 | Group 142 pm_hpmcount2 |
| PM_FPU_STF_GRP142 | FPU executed store instruction | 1 | Group 142 pm_hpmcount2 |
| PM_INST_DISP_GRP142 | Instructions dispatched | 2 | Group 142 pm_hpmcount2 |
| PM_LSU_LDF_GRP142 | LSU executed Floating Point load instruction | 3 | Group 142 pm_hpmcount2 |
| PM_INST_CMPL_GRP142 | Instructions completed | 4 | Group 142 pm_hpmcount2 |
| PM_RUN_CYC_GRP142 | Run cycles | 5 | Group 142 pm_hpmcount2 |
| PM_CYC_GRP143 | Processor cycles | 0 | Group 143 pm_hpmcount3 |
| PM_INST_DISP_ATTEMPT_GRP143 | Instructions dispatch attempted | 1 | Group 143 pm_hpmcount3 |
| PM_LD_MISS_L1_GRP143 | L1 D cache load misses | 2 | Group 143 pm_hpmcount3 |
| PM_ST_MISS_L1_GRP143 | L1 D cache store misses | 3 | Group 143 pm_hpmcount3 |
| PM_INST_CMPL_GRP143 | Instructions completed | 4 | Group 143 pm_hpmcount3 |
| PM_RUN_CYC_GRP143 | Run cycles | 5 | Group 143 pm_hpmcount3 |
| PM_TLB_MISS_GRP144 | TLB misses | 0 | Group 144 pm_hpmcount4 |
| PM_CYC_GRP144 | Processor cycles | 1 | Group 144 pm_hpmcount4 |
| PM_ST_REF_L1_GRP144 | L1 D cache store references | 2 | Group 144 pm_hpmcount4 |
| PM_LD_REF_L1_GRP144 | L1 D cache load references | 3 | Group 144 pm_hpmcount4 |
| PM_INST_CMPL_GRP144 | Instructions completed | 4 | Group 144 pm_hpmcount4 |
| PM_RUN_CYC_GRP144 | Run cycles | 5 | Group 144 pm_hpmcount4 |
| PM_CYC_GRP145 | Processor cycles | 0 | Group 145 pm_hpmcount5 |
| PM_MRK_FXU_FIN_GRP145 | Marked instruction FXU processing finished | 1 | Group 145 pm_hpmcount5 |
| PM_FXU_FIN_GRP145 | FXU produced a result | 2 | Group 145 pm_hpmcount5 |
| PM_FXU0_FIN_GRP145 | FXU0 produced a result | 3 | Group 145 pm_hpmcount5 |
| PM_INST_CMPL_GRP145 | Instructions completed | 4 | Group 145 pm_hpmcount5 |
| PM_RUN_CYC_GRP145 | Run cycles | 5 | Group 145 pm_hpmcount5 |
| PM_INST_CMPL_GRP146 | Instructions completed | 0 | Group 146 pm_eprof1 |
| PM_CYC_GRP146 | Processor cycles | 1 | Group 146 pm_eprof1 |
| PM_LD_MISS_L1_GRP146 | L1 D cache load misses | 2 | Group 146 pm_eprof1 |
| PM_DC_INV_L2_GRP146 | L1 D cache entries invalidated from L2 | 3 | Group 146 pm_eprof1 |
| PM_INST_CMPL_GRP146 | Instructions completed | 4 | Group 146 pm_eprof1 |
| PM_RUN_CYC_GRP146 | Run cycles | 5 | Group 146 pm_eprof1 |
| PM_MRK_LD_MISS_L1_GRP147 | Marked L1 D cache load misses | 0 | Group 147 pm_eprof2 |
| PM_INST_CMPL_GRP147 | Instructions completed | 1 | Group 147 pm_eprof2 |
| PM_ST_REF_L1_GRP147 | L1 D cache store references | 2 | Group 147 pm_eprof2 |
| PM_LD_REF_L1_GRP147 | L1 D cache load references | 3 | Group 147 pm_eprof2 |
| PM_INST_CMPL_GRP147 | Instructions completed | 4 | Group 147 pm_eprof2 |
| PM_RUN_CYC_GRP147 | Run cycles | 5 | Group 147 pm_eprof2 |
| PM_MRK_ST_MISS_L1_GRP148 | Marked L1 D cache store misses | 0 | Group 148 pm_eprof3 |
| PM_INST_CMPL_GRP148 | Instructions completed | 1 | Group 148 pm_eprof3 |
| PM_INST_DISP_GRP148 | Instructions dispatched | 2 | Group 148 pm_eprof3 |
| PM_ST_MISS_L1_GRP148 | L1 D cache store misses | 3 | Group 148 pm_eprof3 |
| PM_INST_CMPL_GRP148 | Instructions completed | 4 | Group 148 pm_eprof3 |
| PM_RUN_CYC_GRP148 | Run cycles | 5 | Group 148 pm_eprof3 |
It is a capital mistake to theorise before one has data. Insensibly one begins to twist facts to suit theories instead of theories to suit facts.- Sherlock Holmes