MIPS 1004K events

This is a list of MIPS 1004K's CPU's performance counter event types. Please see Programming the MIPS32 1004K Core Family available from www.mips.com

Name	Description	Counters usable	Unit mask options
CYCLES	0-0 Cycles	all
INSTRUCTIONS	1-0 Instructions completed	all
DCACHE_MISSES	11-0 Data cache misses	all
BRANCH_INSNS	2-0 Branch instructions (whether completed or mispredicted)	0
JR_31_INSNS	3-0 JR $31 (return) instructions executed	0
JR_NON_31_INSNS	4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)	0
ITLB_ACCESSES	5-0 Instruction micro-TLB accesses	0
DTLB_ACCESSES	6-0 Data micro-TLB accesses	0
JTLB_INSN_ACCESSES	7-0 Joint TLB instruction accesses	0
JTLB_DATA_ACCESSES	8-0 Joint TLB data (non-instruction) accesses	0
ICACHE_ACCESSES	9-0 Instruction cache accesses	0
DCACHE_ACCESSES	10-0 Data cache accesses	0
STORE_MISS_INSNS	13-0 Cacheable stores that miss in the cache	0
INTEGER_INSNS	14-0 Integer instructions completed	0
LOAD_INSNS	15-0 Load instructions completed (including FP)	0
J_JAL_INSNS	16-0 J/JAL instructions completed	0
NO_OPS_INSNS	17-0 no-ops completed, ie instructions writing $0	0
ALL_STALLS	18-0 Stall cycles, including ALU and IFU	0
SC_INSNS	19-0 SC instructions completed	0
PREFETCH_INSNS	20-0 PREFETCH instructions completed	0
L2_CACHE_WRITEBACKS	21-0 L2 cache lines written back to memory	0
L2_CACHE_MISSES	22-0 L2 cache accesses that missed in the cache	0
EXCEPTIONS_TAKEN	23-0 Exceptions taken	0
CACHE_FIXUP_CYCLES	24-0 Cache fixup cycles (specific to the 34K family microarchitecture)	0
IFU_STALLS	25-0 IFU stall cycles	0
DSP_INSNS	26-0 DSP instructions completed	0
POLICY_EVENTS	28-0 Implementation specific policy manager events	0
ISPRAM_EVENTS	29-0 Implementation specific ISPRAM events	0
COREEXTEND_EVENTS	30-0 Implementation specific CorExtend events	0
YIELD_EVENTS	31-0 Implementation specific yield events	0
ITC_LOADS	32-0 ITC Loads	0
UNCACHED_LOAD_INSNS	33-0 Uncached load instructions	0
FORK_INSNS	34-0 Fork instructions completed	0
CP2_ARITH_INSNS	35-0 CP2 arithmetic instructions completed	0
INTERVENTION_STALLS	36-0 Cache coherence intervention processing stall cycles	0
ICACHE_MISS_STALLS	37-0 Stall cycles due to an instruction cache miss	0
DCACHE_MISS_CYCLES	39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline	0
UNCACHED_STALLS	40-0 Uncached stall cycles	0
MDU_STALLS	41-0 MDU stall cycles	0
CP2_STALLS	42-0 CP2 stall cycles	0
ISPRAM_STALLS	43-0 ISPRAM stall cycles	0
CACHE_INSN_STALLS	44-0 Stall cycless due to CACHE instructions	0
LOAD_USE_STALLS	45-0 Load to use stall cycles	0
INTERLOCK_STALLS	46-0 Stall cycles due to return data from MFC0, RDHWR, and MFTR instructions	0
RELAX_STALLS	47-0 Low power stall cycles (operations) as requested by the policy manager	0
IFU_FB_FULL_REFETCHES	48-0 Refetches due to cache misses while both fill buffers already allocated	0
EJTAG_INSN_TRIGGERS	49-0 EJTAG instruction triggerpoints	0
FSB_LESS_25_FULL	50-0 FSB < 25% full	0
FSB_OVER_50_FULL	51-0 FSB > 50% full	0
LDQ_LESS_25_FULL	52-0 LDQ < 25% full	0
LDQ_OVER_50_FULL	53-0 LDQ > 50% full	0
WBB_LESS_25_FULL	54-0 WBB < 25% full	0
WBB_OVER_50_FULL	55-0 WBB > 50% full	0
INTERVENTION_HIT_COUNT	56-0 External interventions that hit in the cache	0
INVALIDATE_INTERVENTION_COUNT	57-0 External invalidate (i.e. leaving a cache line in the invalid state) interventions	0
EVICTION_COUNT	58-0 Cache lines written back due to cache replacement or non-coherent cache operation	0
MESI_INVAL_COUNT	59-0 MESI protocol transitions into invalid state	0
MESI_MODIFIED_COUNT	60-0 MESI protocol transitions into modified state	0
SELF_INTERVENTION_LATENCY	61-0 Latency from miss detection to self intervention	0
READ_RESPONSE_LATENCY	62-0 Read latency from miss detection until critical dword of response is returned	0
MISPREDICTED_BRANCH_INSNS	2-1 Branch mispredictions	1
JR_31_MISPREDICTIONS	3-1 JR $31 mispredictions	1
JR_31_NO_PREDICTIONS	4-1 JR $31 not predicted (stack mismatch).	1
ITLB_MISSES	5-1 Instruction micro-TLB misses	1
DTLB_MISSES	6-1 Data micro-TLB misses	1
JTLB_INSN_MISSES	7-1 Joint TLB instruction misses	1
JTLB_DATA_MISSES	8-1 Joint TLB data (non-instruction) misses	1
ICACHE_MISSES	9-1 Instruction cache misses	1
DCACHE_WRITEBACKS	10-1 Data cache lines written back to memory	1
LOAD_MISS_INSNS	13-1 Cacheable load instructions that miss in the cache	1
FPU_INSNS	14-1 FPU instructions completed (not including loads/stores)	1
STORE_INSNS	15-1 Stores completed (including FP)	1
MIPS16_INSNS	16-1 MIPS16 instructions completed	1
INT_MUL_DIV_INSNS	17-1 Integer multiply/divide instructions completed	1
REPLAYED_INSNS	18-1 Replayed instructions	1
SC_INSNS_FAILED	19-1 SC instructions completed, but store failed (because the link bit had been cleared)	1
CACHE_HIT_PREFETCH_INSNS	20-1 PREFETCH instructions completed with cache hit	1
L2_CACHE_ACCESSES	21-1 Accesses to the L2 cache	1
L2_CACHE_SINGLE_BIT_ERRORS	22-1 Single bit errors corrected in L2	1
SINGLE_THREADED_CYCLES	23-1 Cycles while one and only one TC is eligible for scheduling	1
REFETCHED_INSNS	24-1 Replayed instructions sent back to IFU to be refetched	1
ALU_STALLS	25-1 ALU stall cycles	1
ALU_DSP_SATURATION_INSNS	26-1 ALU-DSP saturation instructions	1
MDU_DSP_SATURATION_INSNS	27-1 MDU-DSP saturation instructions	1
CP2_EVENTS	28-1 Implementation specific CP2 events	1
DSPRAM_EVENTS	29-1 Implementation specific DSPRAM events	1
ITC_EVENT	31-1 Implementation specific yield event	1
UNCACHED_STORE_INSNS	33-1 Uncached store instructions	1
CP2_TO_FROM_INSNS	35-1 CP2 to/from instructions (moves, control, loads, stores)	1
INTERVENTION_MISS_STALLS	36-1 Cache coherence intervention processing stall cycles due to an earlier miss	1
DCACHE_MISS_STALLS	37-1 Stall cycles due to a data cache miss	1
FSB_INDEX_CONFLICT_STALLS	38-1 FSB (fill/store buffer) index conflict stall cycles	1
L2_CACHE_MISS_CYCLES	39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline	1
ITC_STALLS	40-1 ITC stall cycles	1
FPU_STALLS	41-1 FPU stall cycles	1
COREEXTEND_STALLS	42-1 CorExtend stall cycles	1
DSPRAM_STALLS	43-1 DSPRAM stall cycles	1
ALU_TO_AGEN_STALLS	45-1 ALU to AGEN stall cycles	1
MISPREDICTION_STALLS	46-1 Branch mispredict stall cycles	1
FB_ENTRY_ALLOCATED_CYCLES	48-1 Cycles while at least one IFU fill buffer is allocated	1
EJTAG_DATA_TRIGGERS	49-1 EJTAG Data triggerpoints	1
FSB_25_50_FULL	50-1 FSB 25-50% full	1
FSB_FULL_STALLS	51-1 FSB full pipeline stall cycles	1
LDQ_25_50_FULL	52-1 LDQ 25-50% full	1
LDQ_FULL_STALLS	53-1 LDQ full pipeline stall cycles	1
WBB_25_50_FULL	54-1 WBB 25-50% full	1
WBB_FULL_STALLS	55-1 WBB full pipeline stall cycles	1
INTERVENTION_COUNT	56-1 External interventions	1
INVALIDATE_INTERVENTION_HIT_COUNT	57-1 External invalidate interventions that hit in the cache	1
WRITEBACK_COUNT	58-1 Cache lines written back due to cache replacement or any cache operation (non-coherent, self, or external coherent)	1
MESI_EXCLUSIVE_COUNT	59-1 MESI protocol transitions into exclusive state	1
MESI_SHARED_COUNT	60-1 MESI protocol transitions into shared state	1
SELF_INTERVENTION_COUNT	61-1 Self intervention requests on miss detection	1
READ_RESPONSE_COUNT	62-1 Read requests on miss detection	1