Intel Core Solo/Duo events

This is a list of all Core Solo/Duo CPU's performance counter event types. Please see the Intel Architecture 32 Family Developer's Manual, Volume 3, Appendix A. Oprofile use syntethised events and doen't provide a low-level access to Core hardware, so the Intel manual is usefull mainly for people trying to add new events in Oprofile rather for end-user.

Name	Description	Counters usable	Unit mask options
CPU_CLK_UNHALTED	Unhalted clock cycles	all	0x00: Unhalted core cycles 0x01: Unhalted bus cycles 0x02: Unhalted bus cycles of this core while the other core is halted
INST_RETIRED	number of instructions retired	all
L2_RQSTS	number of L2 requests	all	0x08: (M)odified cache state 0x04: (E)xclusive cache state 0x02: (S)hared cache state 0x01: (I)nvalid cache state 0x0f: All cache states 0x10: HW prefetched line only 0x20: all prefetched line w/o regarding mask 0x10.
LD_BLOCKS	number of store buffer blocks	all
SB_DRAINS	number of store buffer drain cycles	all
MISALIGN_MEM_REF	number of misaligned data memory references	all
SEGMENT_REG_LOADS	number of segment register loads	all
EMON_KNI_PREF_DISPATCHED	number of SSE pre-fetch/weakly ordered insns retired	all	0x00: prefetch NTA 0x01: prefetch T1 0x02: prefetch T2 0x03: weakly-ordered stores
FLOPS	number of computational FP operations executed	0
FP_ASSIST	number of FP exceptions handled by microcode	1
MUL	number of multiplies	1
DIV	number of divides	1
CYCLES_DIV_BUSY	cycles divider is busy	0
L2_ADS	number of L2 address strobes	all
L2_DBUS_BUSY	number of cycles data bus was busy	all
L2_DBUS_BUSY_RD	cycles data bus was busy in xfer from L2 to CPU	all
L2_LINES_IN	number of allocated lines in L2	all
L2_M_LINES_INM	number of modified lines allocated in L2	all
L2_LINES_OUT	number of recovered lines from L2	all
L2_M_LINES_OUTM	number of modified lines removed from L2	all
L2_IFETCH	number of L2 instruction fetches	all	0x08: (M)odified cache state 0x04: (E)xclusive cache state 0x02: (S)hared cache state 0x01: (I)nvalid cache state 0x0f: All cache states 0x10: HW prefetched line only 0x20: all prefetched line w/o regarding mask 0x10.
L2_LD	number of L2 data loads	all	0x08: (M)odified cache state 0x04: (E)xclusive cache state 0x02: (S)hared cache state 0x01: (I)nvalid cache state 0x0f: All cache states 0x10: HW prefetched line only 0x20: all prefetched line w/o regarding mask 0x10.
L2_ST	number of L2 data stores	all	0x08: (M)odified cache state 0x04: (E)xclusive cache state 0x02: (S)hared cache state 0x01: (I)nvalid cache state 0x0f: All cache states 0x10: HW prefetched line only 0x20: all prefetched line w/o regarding mask 0x10.
L2_REJECT_CYCLES	Cycles L2 is busy and rejecting new requests	all	0x08: (M)odified cache state 0x04: (E)xclusive cache state 0x02: (S)hared cache state 0x01: (I)nvalid cache state 0x0f: All cache states 0x10: HW prefetched line only 0x20: all prefetched line w/o regarding mask 0x10.
L2_NO_REQUEST_CYCLES	Cycles there is no request to access L2	all	0x08: (M)odified cache state 0x04: (E)xclusive cache state 0x02: (S)hared cache state 0x01: (I)nvalid cache state 0x0f: All cache states 0x10: HW prefetched line only 0x20: all prefetched line w/o regarding mask 0x10.
EST_TRANS_ALL	Intel(tm) Enhanced SpeedStep(r) Technology transitions	all	0x00: any transitions 0x10: Intel(tm) Enhanced SpeedStep(r) Technology frequency transitions 0x20: any transactions
THERMAL_TRIP	Duration in a thremal trip based on the current core clock	all	0xc0: No unit mask
DCACHE_CACHE_LD	L1 cacheable data read operations	all	0x08: (M)odified cache state 0x04: (E)xclusive cache state 0x02: (S)hared cache state 0x01: (I)nvalid cache state 0x0f: All cache states 0x10: HW prefetched line only 0x20: all prefetched line w/o regarding mask 0x10.
DCACHE_CACHE_ST	L1 cacheable data write operations	all	0x08: (M)odified cache state 0x04: (E)xclusive cache state 0x02: (S)hared cache state 0x01: (I)nvalid cache state 0x0f: All cache states 0x10: HW prefetched line only 0x20: all prefetched line w/o regarding mask 0x10.
DCACHE_CACHE_LOCK	L1 cacheable lock read operations to invalid state	all	0x08: (M)odified cache state 0x04: (E)xclusive cache state 0x02: (S)hared cache state 0x01: (I)nvalid cache state 0x0f: All cache states 0x10: HW prefetched line only 0x20: all prefetched line w/o regarding mask 0x10.
DATA_MEM_REFS	all L1 memory references, cachable and non	all	0x01: No unit mask
DATA_MEM_CACHE_REFS	L1 data cacheable read and write operations	all	0x02: No unit mask
DCACHE_REPL	L1 data cache line replacements	all	0x0f: No unit mask
DCACHE_M_REPL	L1 data M-state cache line allocated	all
DCACHE_M_EVICT	L1 data M-state cache line evicted	all
DCACHE_PEND_MISS	Weighted cycles of L1 miss outstanding	all	0x00: Weighted cycles 0x01: Duration of cycles
DTLB_MISS	Data references that missed TLB	all
SSE_PREF_MISS	SSE instructions that missed all caches	all	0x00: PREFETCHNTA 0x01: PREFETCHT1 0x02: PREFETCHT2 0x03: SSE streaming store instructions
L1_PREF_REQ	L1 prefetch requests due to DCU cache misses	all
BUS_REQ_OUTSTANDING	weighted number of outstanding bus requests	all
BUS_BNR_DRV	External bus cycles this processor is driving BNR pin	all
BUS_DRDY_CLOCKS	External bus cycles DRDY is asserted	all
BUS_LOCK_CLOCKS	External bus cycles LOCK is asserted	all
BUS_DATA_RCV	External bus cycles this processor is receiving data	all	0x40: No unit mask
BUS_TRAN_BRD	number of burst read transactions	all
BUS_TRAN_RFO	number of completed read for ownership transactions	all
BUS_TRAN_WB	number of completed writeback transactions	all	0xc0: No unit mask
BUS_TRAN_IFETCH	number of completed instruction fetch transactions	all
BUS_TRAN_INVAL	number of completed invalidate transactions	all
BUS_TRAN_PWR	number of completed partial write transactions	all
BUS_TRANS_P	number of completed partial transactions	all
BUS_TRANS_IO	number of completed I/O transactions	all
BUS_TRANS_DEF	number of completed defer transactions	all	0x20: No unit mask
BUS_TRAN_BURST	number of completed burst transactions	all	0xc0: No unit mask
BUS_TRAN_MEM	number of completed memory transactions	all	0xc0: No unit mask
BUS_TRAN_ANY	number of any completed bus transactions	all	0xc0: No unit mask
BUS_SNOOPS	External bus cycles	all
DCU_SNOOP_TO_SHARE	DCU snoops to share-state L1 cache line due to L1 misses	all	0x01: No unit mask
BUS_NOT_IN_USE	Number of cycles there is no transaction from the core	all
BUS_SNOOP_STALL	Number of bus cycles during bus snoop stall	all
ICACHE_READS	number of instruction fetches	all
ICACHE_MISSES	number of instruction fetch misses	all
ITLB_MISS	number of ITLB misses	all
IFU_MEM_STALL	cycles instruction fetch pipe is stalled	all
ILD_STALL	cycles instruction length decoder is stalled	all
BR_INST_EXEC	Branch instructions executed (not necessarily retired)	all
BR_MISSP_EXEC	Branch instructions executed that were mispredicted at execution	all
BR_BAC_MISSP_EXEC	Branch instructions executed that were mispredicted at Front End (BAC)	all
BR_CND_EXEC	Conditional Branch instructions executed	all
BR_CND_MISSP_EXEC	Conditional Branch instructions executed that were mispredicted	all
BR_IND_EXEC	Indirect Branch instructions executed	all
BR_IND_MISSP_EXEC	Indirect Branch instructions executed that were mispredicted	all
BR_RET_EXEC	Return Branch instructions executed	all
BR_RET_MISSP_EXEC	Return Branch instructions executed that were mispredicted at Execution	all
BR_RET_BAC_MISSP_EXEC	Branch instructions executed that were mispredicted at Front End (BAC)	all
BR_CALL_EXEC	CALL instruction executed	all
BR_CALL_MISSP_EXEC	CALL instruction executed and miss predicted	all
BR_IND_CALL_EXEC	Indirect CALL instruction executed	all
RESOURCE_STALLS	cycles during resource related stalls	all
MMX_INSTR_EXEC	number of MMX instructions executed (not MOVQ and MOVD)	all
SIMD_SAT_INSTR_EXEC	number of SIMD saturating instructions executed	all
MMX_INSTR_TYPE_EXEC	number of MMX packing instructions	all	0x01: MMX packed multiplies 0x02: MMX packed shifts 0x04: MMX pack operations 0x08: MMX unpack operations 0x10: MMX packed logical 0x20: MMX packed arithmetic 0x3f: all of the above
COMP_FLOP_RET	number of computational FP operations retired	0
UOPS_RETIRED	number of UOPs retired	all
SMC_DETECTED	number of times self-modifying code condition is detected	all
BR_INST_RETIRED	number of branch instructions retired	all
BR_MISS_PRED_RETIRED	number of mispredicted branches retired	all
CYCLES_INT_MASKED	cycles interrupts are disabled	all
CYCLES_INT_PENDING_AND_MASKED	cycles interrupts are disabled with pending interrupts	all
HW_INT_RX	number of hardware interrupts received	all
BR_TAKEN_RETIRED	number of taken branches retired	all
BR_MISS_PRED_TAKEN_RET	number of taken mispredictions branches retired	all
FP_MMX_TRANS	MMX-floating point transitions	all	0x00: MMX->float operations 0x01: float->MMX operations
MMX_ASSIST	number of EMMS instructions executed	all
MMX_INSTR_RET	number of MMX instructions retired	all
INST_DECODED	number of instructions decoded	all
ESP_UOPS	Number of ESP folding instructions decoded	all
EMON_SSE_SSE2_INST_RETIRED	Streaming SIMD Extensions Instructions Retired	all	0x00: SSE Packed Single 0x01: SSE Scalar-Single 0x02: SSE2 Packed-Double 0x03: SSE2 Scalar-Double
EMON_SSE_SSE2_COMP_INST_RETIRED	Computational SSE Instructions Retired	all	0x00: SSE Packed Single 0x01: SSE Scalar-Single 0x02: SSE2 Packed-Double 0x03: SSE2 Scalar-Double
EMON_FUSED_UOPS_RET	Number of retired fused micro-ops	all	0x00: All fused micro-ops 0x01: Only load+Op micro-ops 0x02: Only std+sta micro-ops
EMON_UNFUSION	Number of unfusion events in the ROB, happened on a FP exception to a fused uOp	all
BR_INST_DECODED	number of branch instructions decoded	all
BTB_MISSES	number of branches that miss the BTB	all
BR_BOGUS	number of bogus branches	all
BACLEARS	number of times BACLEAR is asserted	all
EMON_PREF_RQSTS_UP	Number of upward prefetches issued	all
EMON_PREF_RQSTS_DN	Number of downward prefetches issued	all