Intel Broadwell Microarchitecture events

This is a list of all Intel Broadwell Microarchitecture performance counter event types. Please see Intel Architecture Developer's Manual Volume 3B, Appendix A and Intel Architecture Optimization Reference Manual (730795-001).

Name	Description	Counters usable	Unit mask options
CPU_CLK_UNHALTED	Clock cycles when not halted	all
UNHALTED_REFERENCE_CYCLES	Unhalted reference cycles	all	0x01: No unit mask
INST_RETIRED	number of instructions retired	all
LLC_MISSES	Last level cache demand requests from this core that missed the LLC	all	0x41: No unit mask
LLC_REFS	Last level cache demand requests from this core	all	0x4f: No unit mask
BR_INST_RETIRED	number of branch instructions retired	all
BR_MISS_PRED_RETIRED	number of mispredicted branches retired (precise)	all
ld_blocks		all	0x02: (name=store_forward) This event counts how many times the load operation got the true Block-on-Store blocking code preventing store forwarding. This includes cases when: - preceding store conflicts with the load (incomplete overlap); - store forwarding is impossible due to u-arch limitations; - preceding lock RMW operations are not forwarded; - store has the no-forward bit set (uncacheable/page-split/masked stores); - all-blocking stores are used (mostly, fences and port I/O); and others. The most common case is a load blocked due to its address range overlapping with a preceding smaller uncompleted store. Note: This event does not take into account cases of out-of-SW-control (for example, SbTailHit), unknown physical STA, and cases of blocking loads on store due to being non-WB memory type or a lock. These cases are covered by other events. See the table of not supported store forwards in the Optimization Guide. 0x08: (name=no_sr) This event counts the number of times that split load operations are temporarily blocked because all resources for handling the split accesses are in use.
misalign_mem_ref		all	0x01: (name=loads) This event counts speculative cache-line split load uops dispatched to the L1 cache. 0x02: (name=stores) This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.
ld_blocks_partial_address_alias		all	0x01: No unit mask
dtlb_load_misses		all	0x01: (name=miss_causes_a_walk) This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G). 0x02: (name=walk_completed_4k) This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault. 0x10: (name=walk_duration) This event counts the number of cycles while PMH is busy with the page walk. 0x20: (name=stlb_hit_4k) Load misses that miss the DTLB and hit the STLB (4K) 0x0e: (name=walk_completed) Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size. 0x60: (name=stlb_hit) Load operations that miss the first DTLB level but hit the second and do not cause page walks
int_misc_recovery_cycles		all	0x03: No unit mask
uops_issued		all	0x01: (name=any) This event counts the number of Uops issued by the Resource Allocation Table (RAT) to the reservation station (RS). 0x10: (name=flags_merge) Number of flags-merge uops being allocated. Such uops considered perf sensitive; added by GSR u-arch. 0x20: (name=slow_lea) Number of slow LEA uops being allocated. A uop is generally considered SlowLea if it has 3 sources (e.g. 2 sources + immediate) regardless if as a result of LEA instruction or not. 0x40: (name=single_mul) Number of Multiply packed/scalar single precision uops allocated 0x01: (name=stall_cycles) This event counts cycles during which the Resource Allocation Table (RAT) does not issue any Uops to the reservation station (RS) for the current thread.
arith_fpu_div_active		all	0x01: No unit mask
l2_rqsts		all	0x21: (name=demand_data_rd_miss) This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted. 0x41: (name=demand_data_rd_hit) This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted. 0x30: (name=l2_pf_miss) This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache. 0x50: (name=l2_pf_hit) This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types 0xe1: (name=all_demand_data_rd) This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted. 0xe2: (name=all_rfo) This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches. 0xe4: (name=all_code_rd) This event counts the total number of L2 code requests. 0xf8: (name=all_pf) This event counts the total number of requests from the L2 hardware prefetchers. 0x42: (name=rfo_hit) RFO requests that hit L2 cache 0x22: (name=rfo_miss) RFO requests that miss L2 cache 0x44: (name=code_rd_hit) L2 cache hits when fetching instructions, code reads. 0x24: (name=code_rd_miss) L2 cache misses when fetching instructions 0x27: (name=all_demand_miss) Demand requests that miss L2 cache 0xe7: (name=all_demand_references) Demand requests to L2 cache 0x3f: (name=miss) All requests that miss L2 cache 0xff: (name=references) All L2 requests
l2_demand_rqsts_wb_hit		all	0x50: No unit mask
l1d_pend_miss		2	0x01: (name=pending) This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type. 0x01: (name=pending_cycles) This event counts duration of L1D miss outstanding in cycles.
dtlb_store_misses		all	0x01: (name=miss_causes_a_walk) This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G). 0x02: (name=walk_completed_4k) This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault. 0x10: (name=walk_duration) This event counts the number of cycles while PMH is busy with the page walk. 0x20: (name=stlb_hit_4k) Store misses that miss the DTLB and hit the STLB (4K) 0x0e: (name=walk_completed) Store misses in all DTLB levels that cause completed page walks 0x60: (name=stlb_hit) Store operations that miss the first TLB level but hit the second and do not cause page walks
load_hit_pre_hw_pf		all	0x02: No unit mask
ept_walk_cycles		all	0x10: No unit mask
l1d_replacement		all	0x01: No unit mask
tx_mem		all	0x01: (name=abort_conflict) Number of times a TSX line had a cache conflict 0x02: (name=abort_capacity_write) Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow 0x04: (name=abort_hle_store_to_elided_lock) Number of times a TSX Abort was triggered due to a non-release/commit store to lock 0x08: (name=abort_hle_elision_buffer_not_empty) Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty 0x10: (name=abort_hle_elision_buffer_mismatch) Number of times a TSX Abort was triggered due to release/commit but data and address mismatch 0x20: (name=abort_hle_elision_buffer_unsupported_alignment) Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer 0x40: (name=hle_elision_buffer_full) Number of times we could not allocate Lock Buffer
move_elimination		all	0x01: (name=int_eliminated) Number of integer Move Elimination candidate uops that were eliminated. 0x02: (name=simd_eliminated) Number of SIMD Move Elimination candidate uops that were eliminated. 0x04: (name=int_not_eliminated) Number of integer Move Elimination candidate uops that were not eliminated. 0x08: (name=simd_not_eliminated) Number of SIMD Move Elimination candidate uops that were not eliminated.
cpl_cycles		all	0x01: (name=ring0) This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode. 0x02: (name=ring123) This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3. 0x01: (name=ring0_trans) This event counts when there is a transition from ring 1,2 or 3 to ring0.
tx_exec		all	0x01: (name=misc1) Unfriendly TSX abort triggered by a flowmarker 0x02: (name=misc2) Unfriendly TSX abort triggered by a vzeroupper instruction 0x04: (name=misc3) Unfriendly TSX abort triggered by a nest count that is too deep 0x08: (name=misc4) RTM region detected inside HLE 0x10: (name=misc5) # HLE inside HLE+
rs_events		all	0x01: (name=empty_cycles) This event counts cycles during which the reservation station (RS) is empty for the thread. Note: In ST-mode, not active thread should drive 0. This is usually caused by severely costly branch mispredictions, or allocator/FE issues. 0x01: (name=empty_end) Counts end of periods where the Reservation Station (RS) was empty. Could be useful to precisely locate Frontend Latency Bound issues.
offcore_requests_outstanding		all	0x01: (name=demand_data_rd) This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS. Note: A prefetch promoted to Demand is counted from the promotion point. 0x02: (name=demand_code_rd) This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The "Offcore outstanding" state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS. 0x04: (name=demand_rfo) This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS. 0x08: (name=all_data_rd) This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS. 0x01: (name=cycles_with_demand_data_rd) This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). 0x08: (name=cycles_with_data_rd) This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.
lock_cycles		all	0x01: (name=split_lock_uc_lock_duration) This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access. 0x02: (name=cache_lock_duration) This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).
idq		all	0x02: (name=empty) This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty. 0x04: (name=mite_uops) This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may "bypass" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB). 0x08: (name=dsb_uops) This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may "bypass" the IDQ. 0x10: (name=ms_dsb_uops) This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may "bypass" the IDQ. 0x20: (name=ms_mite_uops) This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may "bypass" the IDQ. 0x30: (name=ms_uops) This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may "bypass" the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE. 0x30: (name=ms_cycles) This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may "bypass" the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE. 0x04: (name=mite_cycles) This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may "bypass" the IDQ. 0x08: (name=dsb_cycles) This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may "bypass" the IDQ. 0x10: (name=ms_dsb_cycles) This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may "bypass" the IDQ. 0x10: (name=ms_dsb_occur) This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may "bypass" the IDQ. 0x18: (name=all_dsb_cycles_4_uops) This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may "bypass" the IDQ. 0x18: (name=all_dsb_cycles_any_uops) This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may "bypass" the IDQ. 0x24: (name=all_mite_cycles_4_uops) This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may "bypass" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB). 0x24: (name=all_mite_cycles_any_uops) This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may "bypass" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB). 0x3c: (name=mite_all_uops) This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may "bypass" the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB). 0x30: (name=ms_switches) Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer
icache_misses		all	0x02: No unit mask
itlb_misses		all	0x01: (name=miss_causes_a_walk) This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G). 0x02: (name=walk_completed_4k) This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault. 0x10: (name=walk_duration) This event counts the number of cycles while PMH is busy with the page walk. 0x20: (name=stlb_hit_4k) Core misses that miss the DTLB and hit the STLB (4K) 0x0e: (name=walk_completed) Misses in all ITLB levels that cause completed page walks 0x60: (name=stlb_hit) Operations that miss the first ITLB level but hit the second and do not cause any page walks
ild_stall_lcp		all	0x01: No unit mask
br_inst_exec		all	0xff: (name=all_branches) This event counts both taken and not taken speculative and retired branch instructions. 0x41: (name=nontaken_conditional) This event counts not taken macro-conditional branch instructions. 0x81: (name=taken_conditional) This event counts taken speculative and retired macro-conditional branch instructions. 0x82: (name=taken_direct_jump) This event counts taken speculative and retired macro-conditional branch instructions excluding calls and indirect branches. 0x84: (name=taken_indirect_jump_non_call_ret) This event counts taken speculative and retired indirect branches excluding calls and return branches. 0x88: (name=taken_indirect_near_return) This event counts taken speculative and retired indirect branches that have a return mnemonic. 0x90: (name=taken_direct_near_call) This event counts taken speculative and retired direct near calls. 0xa0: (name=taken_indirect_near_call) This event counts taken speculative and retired indirect calls including both register and memory indirect. 0xc1: (name=all_conditional) This event counts both taken and not taken speculative and retired macro-conditional branch instructions. 0xc2: (name=all_direct_jmp) This event counts both taken and not taken speculative and retired macro-unconditional branch instructions, excluding calls and indirects. 0xc4: (name=all_indirect_jump_non_call_ret) This event counts both taken and not taken speculative and retired indirect branches excluding calls and return branches. 0xc8: (name=all_indirect_near_return) This event counts both taken and not taken speculative and retired indirect branches that have a return mnemonic. 0xd0: (name=all_direct_near_call) This event counts both taken and not taken speculative and retired direct near calls.
br_misp_exec		all	0xff: (name=all_branches) This event counts both taken and not taken speculative and retired mispredicted branch instructions. 0x41: (name=nontaken_conditional) This event counts not taken speculative and retired mispredicted macro conditional branch instructions. 0x81: (name=taken_conditional) This event counts taken speculative and retired mispredicted macro conditional branch instructions. 0x84: (name=taken_indirect_jump_non_call_ret) This event counts taken speculative and retired mispredicted indirect branches excluding calls and returns. 0xc1: (name=all_conditional) This event counts both taken and not taken speculative and retired mispredicted macro conditional branch instructions. 0xc4: (name=all_indirect_jump_non_call_ret) This event counts both taken and not taken mispredicted indirect branches excluding calls and returns. 0xa0: (name=taken_indirect_near_call) Taken speculative and retired mispredicted indirect calls
idq_uops_not_delivered		all	0x01: (name=core) This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding ?4 ? x? when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread; b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); c. Instruction Decode Queue (IDQ) delivers four uops. 0x01: (name=cycles_0_uops_deliv_core) This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4. 0x01: (name=cycles_le_1_uop_deliv_core) This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3. 0x01: (name=cycles_le_2_uop_deliv_core) Cycles with less than 2 uops delivered by the front end 0x01: (name=cycles_le_3_uop_deliv_core) Cycles with less than 3 uops delivered by the front end 0x01: (name=cycles_fe_was_ok) Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.
uops_executed_port		all	0x01: (name=port_0_core) Cycles per core when uops are exectuted in port 0 0x02: (name=port_1_core) Cycles per core when uops are exectuted in port 1 0x04: (name=port_2_core) Cycles per core when uops are dispatched to port 2 0x08: (name=port_3_core) Cycles per core when uops are dispatched to port 3 0x10: (name=port_4_core) Cycles per core when uops are exectuted in port 4 0x20: (name=port_5_core) Cycles per core when uops are exectuted in port 5 0x40: (name=port_6_core) Cycles per core when uops are exectuted in port 6 0x80: (name=port_7_core) Cycles per core when uops are dispatched to port 7 0x01: (name=port_0) This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0. 0x02: (name=port_1) This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1. 0x04: (name=port_2) This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2. 0x08: (name=port_3) This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3. 0x10: (name=port_4) This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4. 0x20: (name=port_5) This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5. 0x40: (name=port_6) This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6. 0x80: (name=port_7) This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.
uops_dispatched_port		all	0x01: (name=port_0) This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 0. 0x02: (name=port_1) This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 1. 0x04: (name=port_2) This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 2. 0x08: (name=port_3) This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 3. 0x10: (name=port_4) This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 4. 0x20: (name=port_5) This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 5. 0x40: (name=port_6) This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 6. 0x80: (name=port_7) This event counts, on the per-thread basis, cycles during which uops are dispatched from the Reservation Station (RS) to port 7.
resource_stalls		all	0x01: (name=any) This event counts resource-related stall cycles. Reasons for stalls can be as follows: - *any* u-arch structure got full (LB, SB, RS, ROB, BOB, LM, Physical Register Reclaim Table (PRRT), or Physical History Table (PHT) slots) - *any* u-arch structure got empty (like INT/SIMD FreeLists) - FPU control word (FPCW), MXCSR and others. This counts cycles that the pipeline backend blocked uop delivery from the front end. 0x04: (name=rs) This event counts stall cycles caused by absence of eligible entries in the reservation station (RS). This may result from RS overflow, or from RS deallocation because of the RS array Write Port allocation scheme (each RS entry has two write ports instead of four. As a result, empty entries could not be used, although RS is not really full). This counts cycles that the pipeline backend blocked uop delivery from the front end. 0x08: (name=sb) This event counts stall cycles caused by the store buffer (SB) overflow (excluding draining from synch). This counts cycles that the pipeline backend blocked uop delivery from the front end. 0x10: (name=rob) This event counts ROB full stall cycles. This counts cycles that the pipeline backend blocked uop delivery from the front end.
cycle_activity		2	0x01: (name=cycles_l2_pending) Counts number of cycles the CPU has at least one pending demand* load request missing the L2 cache. 0x08: (name=cycles_l1d_pending) Counts number of cycles the CPU has at least one pending demand load request missing the L1 data cache. 0x02: (name=cycles_ldm_pending) Counts number of cycles the CPU has at least one pending demand load request (that is cycles with non-completed load waiting for its data from memory subsystem) 0x04: (name=cycles_no_execute) Counts number of cycles nothing is executed on any execution port. 0x05: (name=stalls_l2_pending) Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand* load request missing the L2 cache. (as a footprint) * includes also L1 HW prefetch requests that may or may not be required by demands 0x06: (name=stalls_ldm_pending) Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request. 0x0c: (name=stalls_l1d_pending) Counts number of cycles nothing is executed on any execution port, while there was at least one pending demand load request missing the L1 data cache. 0x08: (name=cycles_l1d_miss) Cycles while L1 cache miss demand load is outstanding. 0x01: (name=cycles_l2_miss) Cycles while L2 cache miss demand load is outstanding. 0x02: (name=cycles_mem_any) Cycles while memory subsystem has an outstanding load. 0x04: (name=stalls_total) Total execution stalls. 0x0c: (name=stalls_l1d_miss) Execution stalls while L1 cache miss demand load is outstanding. 0x05: (name=stalls_l2_miss) Execution stalls while L2 cache miss demand load is outstanding. 0x06: (name=stalls_mem_any) Execution stalls while memory subsystem has an outstanding load.
lsd		all	0x01: (name=uops) Number of Uops delivered by the LSD. Read more on LSD under LSD_REPLAY.REPLAY 0x01: (name=cycles_4_uops) Cycles 4 Uops delivered by the LSD, but didn't come from the decoder 0x01: (name=cycles_active) Cycles Uops delivered by the LSD, but didn't come from the decoder
dsb2mite_switches_penalty_cycles		all	0x02: No unit mask
itlb_itlb_flush		all	0x01: No unit mask
offcore_requests		all	0x01: (name=demand_data_rd) This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore. 0x02: (name=demand_code_rd) This event counts both cacheable and noncachaeble code read requests. 0x04: (name=demand_rfo) This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM. 0x08: (name=all_data_rd) This event counts the demand and prefetch data reads. All Core Data Reads include cacheable "Demands" and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.
uops_executed		all	0x01: (name=thread) Number of uops to be executed per-thread each cycle. 0x02: (name=core) Number of uops executed from any thread 0x01: (name=stall_cycles) This event counts cycles during which no uops were dispatched from the Reservation Station (RS) per thread. 0x01: (name=cycles_ge_1_uop_exec) Cycles where at least 1 uop was executed per-thread 0x01: (name=cycles_ge_2_uops_exec) Cycles where at least 2 uops were executed per-thread 0x01: (name=cycles_ge_3_uops_exec) Cycles where at least 3 uops were executed per-thread 0x01: (name=cycles_ge_4_uops_exec) Cycles where at least 4 uops were executed per-thread
page_walker_loads		all	0x11: (name=dtlb_l1) Number of DTLB page walker hits in the L1+FB 0x21: (name=itlb_l1) Number of ITLB page walker hits in the L1+FB 0x12: (name=dtlb_l2) Number of DTLB page walker hits in the L2 0x22: (name=itlb_l2) Number of ITLB page walker hits in the L2 0x14: (name=dtlb_l3) Number of DTLB page walker hits in the L3 + XSNP 0x24: (name=itlb_l3) Number of ITLB page walker hits in the L3 + XSNP 0x18: (name=dtlb_memory) Number of DTLB page walker hits in Memory
inst_retired		1	0x02: (name=x87) This is a non-precise version (that is, does not use PEBS) of the event that counts FP operations retired. For X87 FP operations that have no exceptions counting also includes flows that have several X87, or flows that use X87 uops in the exception handling. 0x01: (name=prec_dist) This is a precise version (that is, uses PEBS) of the event that counts instructions retired.
other_assists		all	0x08: (name=avx_to_sse) This is a non-precise version (that is, does not use PEBS) of the event that counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable. 0x10: (name=sse_to_avx) This is a non-precise version (that is, does not use PEBS) of the event that counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable. 0x40: (name=any_wb_assist) Number of times any microcode assist is invoked by HW upon uop writeback.
uops_retired		all	0x01: (name=all) This is a non-precise version (that is, does not use PEBS) of the event that counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight. 0x01: (name=all_pebs) Counts all actually retired uops. Counting increments by two for micro-fused uops, and by one for macro-fused and other uops. Maximal increment value for one cycle is eight. 0x02: (name=retire_slots) This is a non-precise version (that is, does not use PEBS) of the event that counts the number of retirement slots used. 0x02: (name=retire_slots_pebs) Counts the number of retirement slots used. 0x01: (name=stall_cycles) This is a non-precise version (that is, does not use PEBS) of the event that counts cycles without actually retired uops. 0x01: (name=total_cycles) Number of cycles using always true condition (uops_ret < 16) applied to non PEBS uops retired event.
machine_clears		all	0x01: (name=cycles) This event counts both thread-specific (TS) and all-thread (AT) nukes. 0x02: (name=memory_ordering) This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following: 1. memory disambiguation, 2. external snoop, or 3. cross SMT-HW-thread snoop (stores) hitting load buffer. 0x04: (name=smc) This event counts self-modifying code (SMC) detected, which causes a machine clear. 0x20: (name=maskmov) Maskmov false fault - counts number of time ucode passes through Maskmov flow due to instruction's mask being 0 while the flow was completed without raising a fault. 0x01: (name=count) Number of machine clears (nukes) of any type.
br_inst_retired		all	0x01: (name=conditional) This is a non-precise version (that is, does not use PEBS) of the event that counts conditional branch instructions retired. 0x01: (name=conditional_pebs) Counts conditional branch instructions retired. 0x02: (name=near_call) This is a non-precise version (that is, does not use PEBS) of the event that counts both direct and indirect near call instructions retired. 0x02: (name=near_call_pebs) Counts both direct and indirect near call instructions retired. 0x08: (name=near_return) This is a non-precise version (that is, does not use PEBS) of the event that counts return instructions retired. 0x08: (name=near_return_pebs) Counts return instructions retired. 0x10: (name=not_taken) This is a non-precise version (that is, does not use PEBS) of the event that counts not taken branch instructions retired. 0x20: (name=near_taken) This is a non-precise version (that is, does not use PEBS) of the event that counts taken branch instructions retired. 0x20: (name=near_taken_pebs) Counts taken branch instructions retired. 0x40: (name=far_branch) This is a non-precise version (that is, does not use PEBS) of the event that counts far branch instructions retired. 0x04: (name=all_branches_pebs) This is a precise version of BR_INST_RETIRED.ALL_BRANCHES that counts all (macro) branch instructions retired.
br_misp_retired		all	0x01: (name=conditional) This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted conditional branch instructions retired. 0x01: (name=conditional_pebs) Counts mispredicted conditional branch instructions retired. 0x04: (name=all_branches_pebs) This is a precise version of BR_MISP_RETIRED.ALL_BRANCHES that counts all mispredicted macro branch instructions retired. 0x20: (name=near_taken) number of near branch instructions retired that were mispredicted and taken. 0x20: (name=near_taken_pebs) number of near branch instructions retired that were mispredicted and taken.
hle_retired		all	0x01: (name=start) Number of times we entered an HLE region; does not count nested transactions 0x02: (name=commit) Number of times HLE commit succeeded 0x04: (name=aborted) Number of times HLE abort was triggered 0x04: (name=aborted_pebs) Number of times HLE abort was triggered 0x08: (name=aborted_misc1) Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details) 0x10: (name=aborted_misc2) Number of times the TSX watchdog signaled an HLE abort 0x20: (name=aborted_misc3) Number of times a disallowed operation caused an HLE abort 0x40: (name=aborted_misc4) Number of times HLE caused a fault 0x80: (name=aborted_misc5) Number of times HLE aborted and was not due to the abort conditions in subevents 3-6
rtm_retired		all	0x01: (name=start) Number of times we entered an RTM region; does not count nested transactions 0x02: (name=commit) Number of times RTM commit succeeded 0x04: (name=aborted) Number of times RTM abort was triggered 0x04: (name=aborted_pebs) Number of times RTM abort was triggered 0x08: (name=aborted_misc1) Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details) 0x10: (name=aborted_misc2) Number of times the TSX watchdog signaled an RTM abort 0x20: (name=aborted_misc3) Number of times a disallowed operation caused an RTM abort 0x40: (name=aborted_misc4) Number of times a RTM caused a fault 0x80: (name=aborted_misc5) Number of times RTM aborted and was not due to the abort conditions in subevents 3-6
fp_assist		all	0x1e: (name=any) This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1. 0x02: (name=x87_output) This is a non-precise version (that is, does not use PEBS) of the event that counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid. 0x04: (name=x87_input) This is a non-precise version (that is, does not use PEBS) of the event that counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid. 0x08: (name=simd_output) This is a non-precise version (that is, does not use PEBS) of the event that counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention. 0x10: (name=simd_input) This is a non-precise version (that is, does not use PEBS) of the event that counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.
rob_misc_events_lbr_inserts		all	0x20: No unit mask
mem_uops_retired		all	0x11: (name=stlb_miss_loads) This is a non-precise version (that is, does not use PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault. 0x11: (name=stlb_miss_loads_pebs) Counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault. 0x12: (name=stlb_miss_stores) This is a non-precise version (that is, does not use PEBS) of the event that counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault. 0x12: (name=stlb_miss_stores_pebs) Counts store uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault. 0x21: (name=lock_loads) This is a non-precise version (that is, does not use PEBS) of the event that counts load uops with locked access retired to the architected path. 0x21: (name=lock_loads_pebs) Counts load uops with locked access retired to the architected path. 0x41: (name=split_loads) This is a non-precise version (that is, does not use PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). 0x41: (name=split_loads_pebs) Counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). 0x42: (name=split_stores) This is a non-precise version (that is, does not use PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). 0x42: (name=split_stores_pebs) Counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K). 0x81: (name=all_loads) This is a non-precise version (that is, does not use PEBS) of the event that counts load uops retired to the architected path with a filter on bits 0 and 1 applied. Note: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches. 0x81: (name=all_loads_pebs) Counts load uops retired to the architected path with a filter on bits 0 and 1 applied. Note: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches. 0x82: (name=all_stores) This is a non-precise version (that is, does not use PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied. Note: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement. 0x82: (name=all_stores_pebs) Counts store uops retired to the architected path with a filter on bits 0 and 1 applied. Note: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement.
mem_load_uops_retired		all	0x01: (name=l1_hit) This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the nearest-level (L1) cache. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source 0x01: (name=l1_hit_pebs) Counts retired load uops which data sources were hits in the nearest-level (L1) cache. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source 0x02: (name=l2_hit) This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache. 0x02: (name=l2_hit_pebs) Counts retired load uops which data sources were hits in the mid-level (L2) cache. 0x04: (name=l3_hit) This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required. 0x04: (name=l3_hit_pebs) Counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required. 0x08: (name=l1_miss) This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source. 0x08: (name=l1_miss_pebs) Counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source. 0x10: (name=l2_miss) This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source. 0x10: (name=l2_miss_pebs) Counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source. 0x20: (name=l3_miss) Miss in last-level (L3) cache. Excludes Unknown data-source. 0x20: (name=l3_miss_pebs) Miss in last-level (L3) cache. Excludes Unknown data-source. 0x40: (name=hit_lfb) This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. 0x40: (name=hit_lfb_pebs) Counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready. Note: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.
mem_load_uops_l3_hit_retired		all	0x01: (name=xsnp_miss) This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache. 0x01: (name=xsnp_miss_pebs) Counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache. 0x02: (name=xsnp_hit) This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache. 0x02: (name=xsnp_hit_pebs) Counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache. 0x04: (name=xsnp_hitm) This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3). 0x04: (name=xsnp_hitm_pebs) Counts retired load uops which data sources were HitM responses from a core on same socket (shared L3). 0x08: (name=xsnp_none) This is a non-precise version (that is, does not use PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required. 0x08: (name=xsnp_none_pebs) Counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.
mem_load_uops_l3_miss_retired		all	0x01: (name=local_dram) Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI) 0x01: (name=local_dram_pebs) Retired load uop whose Data Source was: local DRAM either Snoop not needed or Snoop Miss (RspI)
baclears_any		all	0x1f: No unit mask
l2_trans		all	0x80: (name=all_requests) This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on. 0x01: (name=demand_data_rd) This event counts Demand Data Read requests that access L2 cache, including rejects. 0x02: (name=rfo) This event counts Read for Ownership (RFO) requests that access L2 cache. 0x04: (name=code_rd) This event counts the number of L2 cache accesses when fetching instructions. 0x08: (name=all_pf) This event counts L2 or L3 HW prefetches that access L2 cache including rejects. 0x10: (name=l1d_wb) This event counts L1D writebacks that access L2 cache. 0x20: (name=l2_fill) This event counts L2 fill requests that access L2 cache. 0x40: (name=l2_wb) This event counts L2 writebacks that access L2 cache.
l2_lines_in		all	0x07: (name=all) This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects. 0x01: (name=i) This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects. 0x02: (name=s) This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects. 0x04: (name=e) This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.
l2_lines_out_demand_clean		all	0x05: No unit mask