This is a list of all Intel Atom's performance counter event types. Please see the Intel Architecture 32 Family Developer's Manual, Volume 3, Appendix A.
| Name | Description | Counters usable | Unit mask options |
| CPU_CLK_UNHALTED | Clock cycles when not halted | 0, 1 |
0x00: (name=core_p) Core cycles when core is not halted
0x01: (name=bus) Bus cycles when core is not halted 0x02: (name=no_other) Bus cycles when core is active and the other is halted |
| UNHALTED_REFERENCE_CYCLES | Unhalted reference cycles | 0, 1 |
0x01: No unit mask
|
| INST_RETIRED | number of instructions retired | 0, 1 |
0x01: No unit mask
|
| LLC_MISSES | Last level cache demand requests from this core that missed the LLC | 0, 1 |
0x41: No unit mask
|
| LLC_REFS | Last level cache demand requests from this core | 0, 1 |
0x4f: No unit mask
|
| BR_INST_RETIRED | number of branch instructions retired | 0, 1 |
0x00: (name=any) Retired branch instructions
0x01: (name=pred_not_taken) Retired branch instructions that were predicted not-taken 0x02: (name=mispred_not_taken) Retired branch instructions that were mispredicted not-taken 0x04: (name=pred_taken) Retired branch instructions that were predicted taken 0x08: (name=mispred_taken) Retired branch instructions that were mispredicted taken 0x0a: mispred Retired mispredicted branch instructions (precise event) 0x0c: taken Retired taken branch instructions 0x0f: any1 Retired branch instructions |
| BR_MISS_PRED_RETIRED | number of mispredicted branches retired (precise) | 0, 1 | |
| STORE_FORWARDS | Good store forwards | 0, 1 |
0x81: (name=good) Good store forwards
|
| SEGMENT_REG_LOADS | Number of segment register loads | 0, 1 |
0x00: (name=any) Number of segment register loads
|
| PREFETCH | Streaming SIMD Extensions (SSE) Prefetch instructions executed | 0, 1 |
0x01: (name=prefetcht0) Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed
0x06: (name=sw_l2) Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed 0x08: (name=prefetchnta) Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed |
| DATA_TLB_MISSES | Memory accesses that missed the DTLB | 0, 1 |
0x07: (name=dtlb_miss) Memory accesses that missed the DTLB
0x05: (name=dtlb_miss_ld) DTLB misses due to load operations 0x09: (name=l0_dtlb_miss_ld) L0_DTLB misses due to load operations 0x06: (name=dtlb_miss_st) DTLB misses due to store operations |
| PAGE_WALKS | Page walks | 0, 1 |
0x03: (name=walks) Number of page-walks executed
0x03: (name=cycles) Duration of page-walks in core cycles |
| X87_COMP_OPS_EXE | Floating point computational micro-ops | 0, 1 |
0x01: (name=s) Floating point computational micro-ops executed
0x81: (name=ar) Floating point computational micro-ops retired |
| FP_ASSIST | Floating point assists | 0, 1 |
0x81: (name=ar) Floating point assists
|
| MUL | Multiply operations | 0, 1 |
0x01: (name=s) Multiply operations executed
0x81: (name=ar) Multiply operations retired |
| DIV | Divide operations | 0, 1 |
0x01: (name=s) Divide operations executed
0x81: (name=ar) Divide operations retired |
| CYCLES_DIV_BUSY | Cycles the driver is busy | 0, 1 |
0x01: No unit mask
|
| CORE | Cycles L2 address bus is in use | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. |
| L2_DBUS_BUSY | Cycles the L2 cache data bus is busy | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. |
| L2_LINES_IN | L2 cache misses | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x60: (name=all) All inclusive 0x20: (name=hw) Hardware prefetch only 0x00: (name=exclude_hw) Exclude hardware prefetch |
| L2_M_LINES_IN | L2 cache line modifications | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. |
| L2_LINES_OUT | L2 cache lines evicted | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x60: (name=all) All inclusive 0x20: (name=hw) Hardware prefetch only 0x00: (name=exclude_hw) Exclude hardware prefetch |
| L2_M_LINES_OUT | Modified lines evicted from the L2 cache | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x60: (name=all) All inclusive 0x20: (name=hw) Hardware prefetch only 0x00: (name=exclude_hw) Exclude hardware prefetch |
| L2_IFETCH | L2 cacheable instruction fetch requests | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x08: (name=modified) Counts modified state 0x04: (name=exclusive) Counts exclusive state 0x02: (name=shared) Counts shared state 0x01: (name=invalid) Counts invalid state |
| L2_LD | L2 cache reads | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x60: (name=all) All inclusive 0x20: (name=hw) Hardware prefetch only 0x00: (name=exclude_hw) Exclude hardware prefetch 0x08: (name=modified) Counts modified state 0x04: (name=exclusive) Counts exclusive state 0x02: (name=shared) Counts shared state 0x01: (name=invalid) Counts invalid state |
| L2_ST | L2 store requests | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x08: (name=modified) Counts modified state 0x04: (name=exclusive) Counts exclusive state 0x02: (name=shared) Counts shared state 0x01: (name=invalid) Counts invalid state |
| L2_LOCK | L2 locked accesses | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x08: (name=modified) Counts modified state 0x04: (name=exclusive) Counts exclusive state 0x02: (name=shared) Counts shared state 0x01: (name=invalid) Counts invalid state |
| L2_RQSTS | L2 cache requests | 0, 1 |
0x41: (name=i_state) L2 cache demand requests from this core that missed the L2
0x4f: mesi L2 cache demand requests from this core 0x180: (name=all) All cores. 0x80: (name=this) This Core. 0x60: (name=all) All inclusive 0x20: (name=hw) Hardware prefetch only 0x00: (name=exclude_hw) Exclude hardware prefetch 0x08: (name=modified) Counts modified state 0x04: (name=exclusive) Counts exclusive state 0x02: (name=shared) Counts shared state 0x01: (name=invalid) Counts invalid state |
| L2_REJECT_BUSQ | Rejected L2 cache requests | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x60: (name=all) All inclusive 0x20: (name=hw) Hardware prefetch only 0x00: (name=exclude_hw) Exclude hardware prefetch 0x08: (name=modified) Counts modified state 0x04: (name=exclusive) Counts exclusive state 0x02: (name=shared) Counts shared state 0x01: (name=invalid) Counts invalid state |
| L2_NO_REQ | Cycles no L2 cache requests are pending | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. |
| EIST_TRANS | Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions | 0, 1 | |
| THERMAL_TRIP | Number of thermal trips | 0, 1 |
0xc0: (name=thermal_trip) Number of thermal trips.
|
| L1D_CACHE | L1d Cache accesses | 0, 1 |
0x21: (name=ld) L1 Cacheable Data Reads
0x22: (name=st) L1 Cacheable Data Writes |
| BUS_REQUEST_OUTSTANDING | Outstanding cacheable data read bus requests duration | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x00: (name=this) This agent 0x40: (name=any) Include any agents |
| BUS_BNR_DRV | Number of Bus Not Ready signals asserted | 0, 1 |
0x00: (name=this) This agent
0x40: (name=any) Include any agents |
| BUS_DRDY_CLOCKS | Bus cycles when data is sent on the bus | 0, 1 |
0x00: (name=this) This agent
0x40: (name=any) Include any agents |
| BUS_LOCK_CLOCKS | Bus cycles when a LOCK signal is asserted. | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x00: (name=this) This agent 0x40: (name=any) Include any agents |
| BUS_DATA_RCV | Bus cycles while processor receives data | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. |
| BUS_TRANS_BRD | Burst read bus transactions | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x00: (name=this) This agent 0x40: (name=any) Include any agents |
| BUS_TRANS_RFO | RFO bus transactions | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x00: (name=this) This agent 0x40: (name=any) Include any agents |
| BUS_TRANS_WB | Explicit writeback bus transactions | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x00: (name=this) This agent 0x40: (name=any) Include any agents |
| BUS_TRANS_IFETCH | Instruction-fetch bus transactions. | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x00: (name=this) This agent 0x40: (name=any) Include any agents |
| BUS_TRANS_INVAL | Invalidate bus transactions | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x00: (name=this) This agent 0x40: (name=any) Include any agents |
| BUS_TRANS_PWR | Partial write bus transaction. | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x00: (name=this) This agent 0x40: (name=any) Include any agents |
| BUS_TRANS_P | Partial bus transactions | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x00: (name=this) This agent 0x40: (name=any) Include any agents |
| BUS_TRANS_IO | IO bus transactions | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x00: (name=this) This agent 0x40: (name=any) Include any agents |
| BUS_TRANS_DEF | Deferred bus transactions | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x00: (name=this) This agent 0x40: (name=any) Include any agents |
| BUS_TRANS_BURST | Burst (full cache-line) bus transactions. | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x00: (name=this) This agent 0x40: (name=any) Include any agents |
| BUS_TRANS_MEM | Memory bus transactions | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x00: (name=this) This agent 0x40: (name=any) Include any agents |
| BUS_TRANS_ANY | All bus transactions | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x00: (name=this) This agent 0x40: (name=any) Include any agents |
| EXT_SNOOP | External snoops | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x08: (name=modified) Counts modified state 0x04: (name=exclusive) Counts exclusive state 0x02: (name=shared) Counts shared state 0x01: (name=invalid) Counts invalid state |
| BUS_HIT_DRV | HIT signal asserted | 0, 1 |
0x00: (name=this) This agent
0x40: (name=any) Include any agents |
| BUS_HITM_DRV | HITM signal asserted | 0, 1 |
0x00: (name=this) This agent
0x40: (name=any) Include any agents |
| BUSQ_EMPTY | Bus queue is empty | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. |
| SNOOP_STALL_DRV | Bus stalled for snoops | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. 0x00: (name=this) This agent 0x40: (name=any) Include any agents |
| BUS_IO_WAIT | IO requests waiting in the bus queue | 0, 1 |
0x180: (name=all) All cores.
0x80: (name=this) This Core. |
| ICACHE | Instruction cache accesses | 0, 1 |
0x03: (name=accesses) Instruction fetches
0x02: (name=misses) Icache miss |
| ITLB | ITLB events | 0, 1 |
0x04: (name=flush) ITLB flushes
0x02: (name=misses) ITLB misses |
| MACRO_INSTS | instructions decoded | 0, 1 |
0x02: (name=cisc_decoded) CISC macro instructions decoded
0x03: (name=all_decoded) All Instructions decoded |
| SIMD_UOPS_EXEC | SIMD micro-ops executed | 0, 1 |
0x00: (name=s) SIMD micro-ops executed (excluding stores)
0x80: (name=ar) SIMD micro-ops retired (excluding stores) |
| SIMD_SAT_UOP_EXEC | SIMD saturated arithmetic micro-ops executed | 0, 1 |
0x00: (name=s) SIMD saturated arithmetic micro-ops executed
0x80: (name=ar) SIMD saturated arithmetic micro-ops retired |
| SIMD_UOP_TYPE_EXEC | SIMD packed microops executed | 0, 1 |
0x01: (name=s) SIMD packed multiply microops executed
0x81: (name=ar) SIMD packed multiply microops retired 0x02: (name=s) SIMD packed shift micro-ops executed 0x82: (name=ar) SIMD packed shift micro-ops retired 0x04: (name=s) SIMD pack micro-ops executed 0x84: (name=ar) SIMD pack micro-ops retired 0x08: (name=s) SIMD unpack micro-ops executed 0x88: (name=ar) SIMD unpack micro-ops retired 0x10: (name=s) SIMD packed logical microops executed 0x90: (name=ar) SIMD packed logical microops retired 0x20: (name=s) SIMD packed arithmetic micro-ops executed 0xa0: ar SIMD packed arithmetic micro-ops retired |
| UOPS_RETIRED | Micro-ops retired | 0, 1 |
0x10: (name=any) Micro-ops retired
|
| MACHINE_CLEARS | Self-Modifying Code detected | 0, 1 |
0x01: No unit mask
|
| CYCLES_INT_MASKED | Cycles during which interrupts are disabled | 0, 1 |
0x01: (name=cycles_int_masked) Cycles during which interrupts are disabled
0x02: (name=cycles_int_pending_and_masked) Cycles during which interrupts are pending and disabled |
| SIMD_INST_RETIRED | Retired Streaming SIMD Extensions (SSE) instructions | 0, 1 |
0x01: (name=packed_single) Retired Streaming SIMD Extensions (SSE) packed-single instructions
0x02: (name=scalar_single) Retired Streaming SIMD Extensions (SSE) scalar-single instructions 0x04: (name=packed_double) Retired Streaming SIMD Extensions 2 (SSE2) packed-double instructions 0x08: (name=scalar_double) Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions 0x10: (name=vector) Retired Streaming SIMD Extensions 2 (SSE2) vector instructions 0x1f: any Retired Streaming SIMD instructions |
| HW_INT_RCV | Hardware interrupts received | 0, 1 | |
| SIMD_COMP_INST_RETIRED | Retired computational Streaming SIMD Extensions (SSE) instructions. | 0, 1 |
0x01: (name=packed_single) Retired computational Streaming SIMD Extensions (SSE) packed-single instructions
0x02: (name=scalar_single) Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions 0x04: (name=packed_double) Retired computational Streaming SIMD Extensions 2 (SSE2) packed-double instructions 0x08: (name=scalar_double) Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions |
| MEM_LOAD_RETIRED | Retired loads | 0, 1 |
0x01: (name=l2_hit) Retired loads that hit the L2 cache (precise event)
0x02: (name=l2_miss) Retired loads that miss the L2 cache (precise event) 0x04: (name=dtlb_miss) Retired loads that miss the DTLB (precise event) |
| SIMD_ASSIST | SIMD assists invoked | 0, 1 | |
| SIMD_INSTR_RETIRED | SIMD Instructions retired | 0, 1 | |
| SIMD_SAT_INSTR_RETIRED | Saturated arithmetic instructions retired | 0, 1 | |
| BR_INST_DECODED | Branch instructions decoded | 0, 1 | |
| BOGUS_BR | Bogus branches | 0, 1 | |
| BACLEARS | BACLEARS asserted | 0, 1 |
0x01: No unit mask
|
Measurement is a crucial component of performance improvement since reasoning and intuition are fallible guides and must be supplemented with tools like timing commands and profilers.- The Practice of Programming, Brian W. Kernighan and Rob Pike