APM X-Gene events

This is a list of all APM X-Gene's performance counter event types. Please see ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile DDI (ARM DDI0487A.a).

Name	Description	Counters usable	Unit mask options
SW_INCR	Instruction architecturally executed, condition code check pass, software increment	all
L1I_CACHE_REFILL	Level 1 instruction cache refill	all
L1I_TLB_REFILL	Level 1 instruction TLB refill	all
L1D_CACHE_REFILL	Level 1 data cache refill	all
L1D_CACHE	Level 1 data cache access	all
L1D_TLB_REFILL	Level 1 data TLB refill	all
INST_RETIRED	Instruction architecturally executed	all
EXC_TAKEN	Exception taken	all
EXC_RETURN	Instruction architecturally executed, condition code check pass, exception return	all
CID_WRITE_RETIRED	Instruction architecturally executed, condition code check pass, write to CONTEXTIDR	all
BR_MIS_PRED	Mispredicted or not predicted branch speculatively executed	all
CPU_CYCLES	Cycle	all
BR_PRED	Predictable branch speculatively executed	all
MEM_ACCESS	Data memory access	all
L1I_CACHE	Level 1 instruction cache access	all
L2D_CACHE	Level 2 data cache access	all
L2D_CACHE_REFILL	Level 2 data cache refill	all
L2D_CACHE_WB	Level 2 data cache write-back	all
BUS_ACCESS	Bus access	all
MEMORY_ERROR	Local memory error	all
INST_SPEC	Operation speculatively executed	all
TTBR_WRITE_RETIRED	Instruction architecturally executed, condition code check pass, write to TTBR	all
L1D_CACHE_LD	L1 data cache access - Read	all
L1D_CACHE_ST	L1 data cache access - Write	all
L1D_CACHE_REFILL_LD	L1 data cache refill - Read	all
L1D_CACHE_INVAL	L1 data cache invalidate	all
L1D_TLB_REFILL_LD	L1 data TLB refill - Read	all
L1D_TLB_REFILL_ST	L1 data TLB refill - Write	all
L2D_CACHE_LD	L2 data cache access - Read	all
L2D_CACHE_ST	L2 data cache access - Write	all
L2D_CACHE_REFILL_LD	L2 data cache refill - Read	all
L2D_CACHE_REFILL_ST	L2 data cache refill - Write	all
L2D_CACHE_WB_VICTIM	L2 data cache write-back - victim	all
L2D_CACHE_WB_CLEAN	L2 data cache write-back - Cleaning and coherency	all
L2D_CACHE_INVAL	L2 data cache invalidate	all
BUS_ACCESS_LD	Bus access - Read	all
BUS_ACCESS_ST	Bus access - Write	all
BUS_ACCESS_SHARED	Bus access - Normal, cacheable, sharable	all
BUS_ACCESS_NOT_SHARED	Bus access - Not normal, cacheable, sharable	all
BUS_ACCESS_NORMAL	Bus access - Normal	all
BUS_ACCESS_PERIPH	Bus access - Peripheral	all
MEM_ACCESS_LD	Data memory access - Read	all
MEM_ACCESS_ST	Data memory access - write	all
UNALIGNED_LD_SPEC	Unaligned access - Read	all
UNALIGNED_ST_SPEC	Unaligned access - Write	all
UNALIGNED_LDST_SPEC	Unaligned access	all
LDREX_SPEC	Exclusive operation speculatively executed - Load exclusive	all
STREX_PASS_SPEC	Exclusive operation speculative executed - Store exclusive pass	all
STREX_FAIL_SPEC	Exclusive operation speculative executed - Store exclusive fail	all
STREX_SPEC	Exclusive operation speculatively executed - Store exclusive	all
LD_SPEC	Operation speculatively executed - Load	all
ST_SPEC	Operation speculatively executed - Store	all
LDST_SPEC	Operation speculatively executed - Load or store	all
DP_SPEC	Operation speculatively executed - Integer data processing	all
ASE_SPEC	Operation speculatively executed - Advanced SIMD	all
VFP_SPEC	Operation speculatively executed - FP	all
PC_WRITE_SPEC	Operation speculatively executed - Software change of PC	all
BR_IMMED_SPEC	Branch speculative executed - Immediate branch	all
BR_RETURN_SPEC	Branch speculative executed - Procedure return	all
BR_INDIRECT_SPEC	Branch speculative executed - Indirect branch	all
ISB_SPEC	Barrier speculatively executed - ISB	all
DSB_SPEC	Barrier speculatively executed - DSB	all
DMB_SPEC	Barrier speculatively executed - DMB	all
EXC_UNDEF	Exception taken, other synchronous	all
EXC_SVC	Exception taken, Supervisor Call	all
EXC_PABORT	Exception taken, Instruction Abort	all
EXC_DABORT	Exception taken, Data Abort or SError	all
EXC_IRQ	Exception taken, IRQ	all
EXC_FIQ	Exception taken, FIQ	all
EXC_HVC	Exception taken, Hypervisor Call	all
EXC_TRAP_PABORT	Exception taken, Instruction Abort not taken locally	all
EXC_TRAP_DABORT	Exception taken, Data Abort or SError not taken locally	all
EXC_TRAP_OTHER	Exception taken, other traps not taken locally	all
EXC_TRAP_IRQ	Exception taken, IRQ not taken locally	all
EXC_TRAP_FIQ	Exception taken, FIQ not taken locally	all
RC_LD_SPEC	Release consistency instruction speculatively executed - Load Acquire	all
RC_ST_SPEC	Release consistency instruction speculatively executed - Store Release	all
NOP_SPEC	Operation speculatively executed - NOP	all
FSU_CLOCK_OFF_CYCLES	FSU clocking gated off cycle	all
BTB_MIS_PRED	BTB misprediction	all
ITB_MISS	ITB miss	all
DTB_MISS	DTB miss	all
L1D_CACHE_LATE_MISS	L1 data cache late miss	all
L1D_CACHE_PREFETCH	L1 data cache prefetch request	all
L2D_CACHE_PREFETCH	L2 data prefetch request	all
DECODE_STALL	Decode starved for instruction cycle	all
DISPATCH_STALL	Op dispatch stalled cycle	all
IXA_STALL	IXA Op non-issue	all
IXB_STALL	IXB Op non-issue	all
BX_STALL	BX Op non-issue	all
LX_STALL	LX Op non-issue	all
SX_STALL	SX Op non-issue	all
FX_STALL	FX Op non-issue	all
WAIT_CYCLES	Wait state cycle	all
L1_STAGE2_TLB_REFILL	L1 stage-2 TLB refill	all
PAGE_WALK_L0_STAGE1_HIT	Page Walk Cache level-0 stage-1 hit	all
PAGE_WALK_L1_STAGE1_HIT	Page Walk Cache level-1 stage-1 hit	all
PAGE_WALK_L2_STAGE1_HIT	Page Walk Cache level-2 stage-1 hit	all
PAGE_WALK_L1_STAGE2_HIT	Page Walk Cache level-1 stage-2 hit	all
PAGE_WALK_L2_STAGE2_HIT	Page Walk Cache level-2 stage-2 hit	all