ARM V8 Cortex-A57 events

This is a list of all ARM V8 Cortex-A57's performance counter event types. Please see Cortex-A57 MPCore Technical Reference Manual Cortex A57 DDI (ARM DDI 0488D, revision r1p1).

Name	Description	Counters usable	Unit mask options
SW_INCR	Instruction architecturally executed, condition code check pass, software increment	all
L1I_CACHE_REFILL	Level 1 instruction cache refill	all
L1I_TLB_REFILL	Level 1 instruction TLB refill	all
L1D_CACHE_REFILL	Level 1 data cache refill	all
L1D_CACHE	Level 1 data cache access	all
L1D_TLB_REFILL	Level 1 data TLB refill	all
LD_RETIRED	Instruction architecturally executed, condition code check pass, load	all
ST_RETIRED	Instruction architecturally executed, condition code check pass, store	all
INST_RETIRED	Instruction architecturally executed	all
EXC_TAKEN	Exception taken	all
EXC_RETURN	Instruction architecturally executed, condition code check pass, exception return	all
CID_WRITE_RETIRED	Instruction architecturally executed, condition code check pass, write to CONTEXTIDR	all
PC_WRITE_RETIRED	Instruction architecturally executed, condition code check pass, software change of the PC	all
BR_IMMED_RETIRED	Instruction architecturally executed, immediate branch	all
BR_RETURN_RETIRED	Instruction architecturally executed, condition code check pass, procedure return	all
UNALIGNED_LDST_RETIRED	Instruction architecturally executed, condition code check pass, unaligned load or store	all
BR_MIS_PRED	Mispredicted or not predicted branch speculatively executed	all
CPU_CYCLES	Cycle	all
BR_PRED	Predictable branch speculatively executed	all
MEM_ACCESS	Data memory access	all
L1I_CACHE	Level 1 instruction cache access	all
L1D_CACHE_WB	Level 1 data cache write-back	all
L2D_CACHE	Level 2 data cache access	all
L2D_CACHE_REFILL	Level 2 data cache refill	all
L2D_CACHE_WB	Level 2 data cache write-back	all
BUS_ACCESS	Bus access	all
MEMORY_ERROR	Local memory error	all
INST_SPEC	Operation speculatively executed	all
TTBR_WRITE_RETIRED	Instruction architecturally executed, condition code check pass, write to TTBR	all
BUS_CYCLES	Bus cycle	all
L1D_CACHE_ALLOCATE	Level 1 data cache allocation without refill	all
L2D_CACHE_ALLOCATE	Level 2 data cache allocation without refill	all
L1D_CACHE_LD	Level 1 data cache access - Read	all
L1D_CACHE_ST	Level 1 data cache access - Write	all
L1D_CACHE_REFILL_LD	Level 1 data cache refill - Read	all
L1D_CACHE_REFILL_ST	Level 1 data cache refill - Write	all
L1D_CACHE_WB_VICTIM	Level 1 data cache Write-back - Victim	all
L1D_CACHE_WB_CLEAN	Level 1 data cache Write-back - Cleaning event:and coherency	all
L1D_CACHE_INVAL	Level 1 data cache invalidate	all
L1D_TLB_REFILL_LD	Level 1 data TLB refill - Read	all
L1D_TLB_REFILL_ST	Level 1 data TLB refill - Write	all
L2D_CACHE_LD	Level 2 data cache access - Read	all
L2D_CACHE_ST	Level 2 data cache access - Write	all
L2D_CACHE_REFILL_LD	Level 2 data cache refill - Read	all
L2D_CACHE_REFILL_ST	Level 2 data cache refill - Write	all
L2D_CACHE_WB_VICTIM	Level 2 data cache Write-back - Victim	all
L2D_CACHE_WB_CLEAN	Level 2 data cache Write-back - Cleaning and coherency	all
L2D_CACHE_INVAL	Level 2 data cache invalidate	all
BUS_ACCESS_LD	Bus access - Read	all
BUS_ACCESS_ST	Bus access - Write	all
BUS_ACCESS_SHARED	Bus access - Normal	all
BUS_ACCESS_NOT_SHARED	Bus access - Not normal	all
BUS_ACCESS_NORMAL	Bus access - Normal	all
BUS_ACCESS_PERIPH	Bus access - Peripheral	all
MEM_ACCESS_LD	Data memory access - Read	all
MEM_ACCESS_ST	Data memory access - Write	all
UNALIGNED_LD_SPEC	Unaligned access - Read	all
UNALIGNED_ST_SPEC	Unaligned access - Write	all
UNALIGNED_LDST_SPEC	Unaligned access	all
LDREX_SPEC	Exclusive operation speculatively executed - LDREX	all
STREX_PASS_SPEC	Exclusive instruction speculatively executed - STREX pass	all
STREX_FAIL_SPEC	Exclusive operation speculatively executed - STREX fail	all
LD_SPEC	Operation speculatively executed - Load	all
ST_SPEC	Operation speculatively executed - Store	all
LDST_SPEC	Operation speculatively executed - Load or store	all
DP_SPEC	Operation speculatively executed - Integer data processing	all
ASE_SPEC	Operation speculatively executed - Advanced SIMD	all
VFP_SPEC	Operation speculatively executed - VFP	all
PC_WRITE_SPEC	Operation speculatively executed - Software change of the PC	all
CRYPTO_SPEC	Operation speculatively executed, crypto data processing	all
BR_IMMED_SPEC	Branch speculatively executed - Immediate branch	all
BR_RETURN_SPEC	Branch speculatively executed - Procedure return	all
BR_INDIRECT_SPEC	Branch speculatively executed - Indirect branch	all
ISB_SPEC	Barrier speculatively executed - ISB	all
DSB_SPEC	Barrier speculatively executed - DSB	all
DMB_SPEC	Barrier speculatively executed - DMB	all
EXC_UNDEF	Exception taken, other synchronous	all
EXC_SVC	Exception taken, Supervisor Call	all
EXC_PABORT	Exception taken, Instruction Abort	all
EXC_DABORT	Exception taken, Data Abort or SError	all
EXC_IRQ	Exception taken, IRQ	all
EXC_FIQ	Exception taken, FIQ	all
EXC_SMC	Exception taken, Secure Monitor Call	all
EXC_HVC	Exception taken, Hypervisor Call	all
EXC_TRAP_PABORT	Exception taken, Instruction Abort not taken locally	all
EXC_TRAP_DABORT	Exception taken, Data Abort, or SError not taken locally	all
EXC_TRAP_OTHER	Exception taken – Other traps not taken locally	all
EXC_TRAP_IRQ	Exception taken, IRQ not taken locally	all
EXC_TRAP_FIQ	Exception taken, FIQ not taken locally	all
RC_LD_SPEC	Release consistency instruction speculatively executed – Load-Acquire	all
RC_ST_SPEC	Release consistency instruction speculatively executed – Store-Release	all