ARM/XScale PMU1 events

This is a list of all ARM/XScale PMU1's performance counter event types. Please See Intel XScale Core Developer's Manual - Chapter 8 Performance Monitoring

Name	Description	Counters usable	Unit mask options
IFU_IFETCH_MISS	number of instruction fetch misses	1, 2
CYCLES_IFU_MEM_STALL	cycles instruction fetch pipe is stalled	1, 2
CYCLES_DATA_STALL	cycles stall occurs for due to data dependency	1, 2
ITLB_MISS	number of ITLB misses	1, 2
DTLB_MISS	number of DTLB misses	1, 2
BR_INST_EXECUTED	branch instruction executed w/ or w/o program flow change	1, 2
BR_INST_MISS_PRED	branch mispredicted	1, 2
INSN_EXECUTED	instruction executed	1, 2
CYCLES_DCACHE_FULL_STALL	cycles in stall due to full dcache	1, 2
DCACHE_FULL_STALL_CNT	number of stalls due to dcache full condition	1
DCACHE_ACCESS	data cache access	1, 2
DCACHE_MISS	data cache miss	1, 2
DCACHE_WB	data cache writeback, 1 event for every half cacheline	1, 2
PC_CHANGE	number of times the program counter was changed without a mode switch	1, 2
BCU_REQUEST	number of time the BCU received a new memory request from the core	1, 2
BCU_FULL	number of cycles the BCUs request queue is full	1, 2
BCU_DRAIN	number of times the BCU queues were drained due to a Drain Write Buffer command or an I/O transaction on a non-cacheable and non-bufferable page	1, 2
BCU_ECC_NO_ELOG	number of times the BCU detected an ECC error, but no ELOG register was available in which to log the error	1, 2
BCU_1_BIT_ERR	number of times the BCU detected a 1-bit error while reading data from the bus	1, 2
RMW	number of times an RMW cycle occurred due to narrow write on ECC-protected memory	1, 2
CPU_CYCLES	clock cycles counter	0