ARM V6 events

This is a list of all ARM V6's performance counter event types. Please see ARM11 Technical Reference Manual.

Name	Description	Counters usable	Unit mask options
IFU_IFETCH_MISS	number of instruction fetch misses	0, 1
CYCLES_IFU_MEM_STALL	cycles instruction fetch pipe is stalled	0, 1
CYCLES_DATA_STALL	cycles stall occurs for due to data dependency	0, 1
ITLB_MISS	number of Instruction MicroTLB misses	0, 1
DTLB_MISS	number of Data MicroTLB misses	0, 1
BR_INST_EXECUTED	branch instruction executed w/ or w/o program flow change	0, 1
BR_INST_MISS_PRED	branch mispredicted	0, 1
INSN_EXECUTED	instructions executed	0, 1
DCACHE_ACCESS	data cache access, cacheable locations	0, 1
DCACHE_ACCESS_ALL	data cache access, all locations	0, 1
DCACHE_MISS	data cache miss	0, 1
DCACHE_WB	data cache writeback, 1 event for every half cacheline	0, 1
PC_CHANGE	number of times the program counter was changed without a mode switch	0, 1
TLB_MISS	Main TLB miss	0, 1
EXP_EXTERNAL	Explict external data access	0, 1
LSU_STALL	cycles stalled because Load Store request queque is full	0, 1
WRITE_DRAIN	Times write buffer was drained	0, 1
ETMEXTOUT0	nuber of cycles ETMEXTOUT[0] signal was asserted	0, 1
ETMEXTOUT1	nuber of cycles ETMEXTOUT[1] signal was asserted	0, 1
ETMEXTOUT_BOTH	nuber of cycles both ETMEXTOUT [0] and [1] were asserted * 2	0, 1
CPU_CYCLES	clock cycles counter	all