This is a list of AMD64 family 15h's CPU's performance counter event types. Please see BIOS and Kernel Developer's Guide for AMD Family 15h Processors.
| Name | Description | Counters usable | Unit mask options |
| DISPATCHED_FPU_OPS | FPU Pipe Assignment | 3 |
0x01: Total number uops assigned to Pipe 0
0x02: Total number uops assigned to Pipe 1 0x04: Total number uops assigned to Pipe 2 0x08: Total number uops assigned to Pipe 3 0x10: Total number dual-pipe uops assigned to Pipe 0 0x20: Total number dual-pipe uops assigned to Pipe 1 0x40: Total number dual-pipe uops assigned to Pipe 2 0x80: Total number dual-pipe uops assigned to Pipe 3 0xff: All ops |
| CYCLES_FPU_EMPTY | FP Scheduler Empty | 3, 4, 5 | |
| RETIRED_SSE_OPS | Retired SSE/BNI Ops | 3 |
0x01: Single Precision add/subtract FLOPS
0x02: Single precision multiply FLOPS 0x04: Single precision divide/square root FLOPS 0x08: Single precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS 0x10: Double precision add/subtract FLOPS 0x20: Double precision multiply FLOPS 0x40: Double precision divide/square root FLOPS 0x80: Double precision multiply-add FLOPS. Multiply-add counts as 2 FLOPS |
| MOVE_SCALAR_OPTIMIZATION | Number of Move Elimination and Scalar Op Optimization | 3 |
0x01: Number of SSE Move Ops
0x02: Number of SSE Move Ops eliminated 0x04: Number of Ops that are candidates for optimization 0x08: Number of Scalar ops optimized |
| RETIRED_SERIALIZING_OPS | Retired Serializing Ops | 3, 4, 5 |
0x01: SSE bottom-executing uops retired
0x02: SSE control word mispredict traps due to mispredictions 0x04: x87 bottom-executing uops retired 0x08: x87 control word mispredict traps due to mispredictions |
| BOTTOM_EXECUTE_OP | Number of Cycles that a Bottom-Execute uop is in the FP Scheduler | 3, 4, 5 | |
| SEGMENT_REGISTER_LOADS | Segment Register Loads | all |
0x01: ES register
0x02: CS register 0x04: SS register 0x08: DS register 0x10: FS register 0x20: GS register 0x40: HS register |
| PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE | Pipeline Restart Due to Self-Modifying Code | all | |
| PIPELINE_RESTART_DUE_TO_PROBE_HIT | Pipeline Restart Due to Probe Hit | all | |
| LOAD_Q_STORE_Q_FULL | Load Queue/Store Queue Full | 0, 1, 2 |
0x01: Cycles that the load buffer is full
0x02: Cycles that the store buffer is full |
| LOCKED_OPS | Locked Operations | all |
0x01: Number of locked instructions executed
0x04: Cycles spent non-speculative phase (including cache miss penalty) 0x08: Cycles waiting for a cache hit (cache miss penalty) |
| RETIRED_CLFLUSH_INSTRUCTIONS | Retired CLFLUSH Instructions | all | |
| RETIRED_CPUID_INSTRUCTIONS | Retired CPUID Instructions | all | |
| LS_DISPATCH | LS Dispatch | all |
0x01: Loads
0x02: Stores 0x04: Load-op-Stores |
| CANCELLED_STORE_TO_LOAD | Canceled Store to Load Forward Operations | all |
0x01: Store is smaller than load or different starting byte but partial overlap
|
| SMIS_RECEIVED | SMIs Received | all | |
| EXECUTED_CFLUSH_INST | Executed CLFLUSH Instructions | all | |
| DATA_CACHE_ACCESSES | Data Cache Accesses | all | |
| DATA_CACHE_MISSES | Data Cache Misses | all |
0x01: First data cache miss or streaming store to a 64B cache line
0x02: First streaming store to a 64B cache line |
| DATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGE | Data Cache Refills from L2 or System | all |
0x01: Fill with good data. (Final valid status is valid)
0x02: Early valid status turned out to be invalid 0x08: Fill with read data error |
| DATA_CACHE_REFILLS_FROM_NORTHBRIDGE | Data Cache Refills from System | 0, 1, 2 | |
| UNIFIED_TLB_HIT | Unified TLB Hit | 0, 1, 2 |
0x01: 4 KB unified TLB hit for data
0x02: 2 MB unified TLB hit for data 0x04: 1 GB unified TLB hit for data 0x10: 4 KB unified TLB hit for instruction 0x20: 2 MB unified TLB hit for instruction 0x40: 1 GB unified TLB hit for instruction 0x07: All DTLB hits 0x70: All ITLB hits 0x77: All DTLB and ITLB hits |
| UNIFIED_TLB_MISS | Unified TLB Miss | 0, 1, 2 |
0x01: 4 KB unified TLB miss for data
0x02: 2 MB unified TLB miss for data 0x04: 1 GB unified TLB miss for data 0x10: 4 KB unified TLB miss for instruction 0x20: 2 MB unified TLB miss for instruction 0x40: 1 GB unified TLB miss for instruction 0x07: All DTLB misses 0x70: All ITLB misses 0x77: All DTLB and ITLB misses |
| MISALIGNED_ACCESSES | Misaligned Accesses | all | |
| PREFETCH_INSTRUCTIONS_DISPATCHED | Prefetch Instructions Dispatched | all |
0x01: Load (Prefetch, PrefetchT0/T1/T2)
0x02: Store (PrefetchW) 0x04: NTA (PrefetchNTA) |
| INEFFECTIVE_SW_PREFETCHES | Ineffective Software Prefetches | all |
0x01: Software prefetch hit in L1 data cache
0x08: Software prefetch hit in the L2 |
| MEMORY_REQUESTS | Memory Requests by Type | 0, 1, 2 |
0x01: Requests to non-cacheable (UC) memory
0x02: Requests to write-combining (WC) memory 0x80: Streaming store (SS) requests |
| DATA_PREFETCHER | Data Prefetcher | 0, 1, 2 |
0x02: Prefetch attempts
|
| MAB_REQS | MAB Requests | 0, 1, 2 |
0x01: MAB ID bit 0
0x02: MAB ID bit 1 0x04: MAB ID bit 2 0x08: MAB ID bit 3 0x10: MAB ID bit 4 0x20: MAB ID bit 5 0x40: MAB ID bit 6 0x80: MAB ID bit 7 |
| MAB_WAIT | MAB Wait Cycles | 0, 1, 2 |
0x01: MAB ID bit 0
0x02: MAB ID bit 1 0x04: MAB ID bit 2 0x08: MAB ID bit 3 0x10: MAB ID bit 4 0x20: MAB ID bit 5 0x40: MAB ID bit 6 0x80: MAB ID bit 7 |
| SYSTEM_READ_RESPONSES | Response From System on Cache Refills | 0, 1, 2 |
0x01: Exclusive
0x02: Modified 0x04: Shared 0x08: Owned 0x10: Data Error 0x20: Modified unwritten |
| OCTWORD_WRITE_TRANSFERS | Octwords Written to System | 0, 1, 2 |
0x01: Octword write transfer
|
| CPU_CLK_UNHALTED | CPU Clocks not Halted | 0, 1, 2 | |
| REQUESTS_TO_L2 | Requests to L2 Cache | 0, 1, 2 |
0x01: IC fill
0x02: DC fill 0x04: TLB fill (page table walks) 0x08: NB probe request 0x10: Canceled request 0x40: L2 cache prefetcher request |
| L2_CACHE_MISS | L2 Cache Misses | 0, 1, 2 |
0x01: IC fill
0x02: DC fill (includes possible replays, whereas PMCx041 does not) 0x04: TLB page table walks 0x10: L2 cache prefetcher request |
| L2_CACHE_FILL_WRITEBACK | L2 Fill/Writeback | 0, 1, 2 |
0x01: L2 fills from system
0x02: L2 Writebacks to system (Clean and Dirty) 0x04: L2 Clean Writebacks to system |
| PAGE_SPLINTERING | Page Splintering | 0, 1, 2 |
0x01: Guest page size is larger than host page size when nested paging is enabled
0x02: Splintering due to MTRRs, IORRs, APIC, TOMs or other special address region 0x04: Host page size is larger than the guest page size |
| L2_PREFETCHER_TRIGGER | L2 Prefetcher Trigger Events | 0, 1, 2 |
0x01: Load L1 miss seen by prefetcher
0x02: Store L1 miss seen by prefetcher |
| INSTRUCTION_CACHE_FETCHES | Instruction Cache Fetches | 0, 1, 2 | |
| INSTRUCTION_CACHE_MISSES | Instruction Cache Misses | 0, 1, 2 | |
| INSTRUCTION_CACHE_REFILLS_FROM_L2 | Instruction Cache Refills from L2 | 0, 1, 2 | |
| INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM | Instruction Cache Refills from System | 0, 1, 2 | |
| L1_ITLB_MISS_AND_L2_ITLB_HIT | L1 ITLB Miss, L2 ITLB Hit | 0, 1, 2 | |
| L1_ITLB_MISS_AND_L2_ITLB_MISS | L1 ITLB Miss, L2 ITLB Miss | 0, 1, 2 |
0x01: Instruction fetches to a 4K page
0x02: Instruction fetches to a 2M page 0x04: Instruction fetches to a 1G page |
| PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE | Pipeline Restart Due to Instruction Stream Probe | 0, 1, 2 | |
| INSTRUCTION_FETCH_STALL | Instruction Fetch Stall | 0, 1, 2 | |
| RETURN_STACK_HITS | Return Stack Hits | 0, 1, 2 | |
| RETURN_STACK_OVERFLOWS | Return Stack Overflows | 0, 1, 2 | |
| INSTRUCTION_CACHE_VICTIMS | Instruction Cache Victims | 0, 1, 2 | |
| INSTRUCTION_CACHE_INVALIDATED | Instruction Cache Lines Invalidated | 0, 1, 2 |
0x01: Non-SMC invalidating probe that missed on in-flight instructions
0x02: Non-SMC invalidating probe that hit on in-flight instructions 0x04: SMC invalidating probe that missed on in-flight instructions 0x08: SMC invalidating probe that hit on in-flight instructions |
| ITLB_RELOADS | ITLB Reloads | 0, 1, 2 | |
| ITLB_RELOADS_ABORTED | ITLB Reloads Aborted | 0, 1, 2 | |
| RETIRED_INSTRUCTIONS | Retired Instructions | all | |
| RETIRED_UOPS | Retired uops | all | |
| RETIRED_BRANCH_INSTRUCTIONS | Retired Branch Instructions | all | |
| RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS | Retired Mispredicted Branch Instructions | all | |
| RETIRED_TAKEN_BRANCH_INSTRUCTIONS | Retired Taken Branch Instructions | all | |
| RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED | Retired Taken Branch Instructions Mispredicted | all | |
| RETIRED_FAR_CONTROL_TRANSFERS | Retired Far Control Transfers | all | |
| RETIRED_BRANCH_RESYNCS | Retired Branch Resyncs | all | |
| RETIRED_NEAR_RETURNS | Retired Near Returns | all | |
| RETIRED_NEAR_RETURNS_MISPREDICTED | Retired Near Returns Mispredicted | all | |
| RETIRED_INDIRECT_BRANCHES_MISPREDICTED | Retired Indirect Branches Mispredicted | all | |
| RETIRED_MMX_FP_INSTRUCTIONS | Retired MMX/FP Instructions | all |
0x01: x87 instructions
0x02: MMX(tm) instructions 0x04: SSE instructions (SSE,SSE2,SSE3,SSSE3,SSE4A,SSE4.1,SSE4.2,AVX,XOP,FMA4) |
| INTERRUPTS_MASKED_CYCLES | Interrupts-Masked Cycles | all | |
| INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING | Interrupts-Masked Cycles with Interrupt Pending | all | |
| INTERRUPTS_TAKEN | Interrupts Taken | all | |
| DECODER_EMPTY | Decoder Empty | 0, 1, 2 | |
| DISPATCH_STALLS | Dispatch Stalls | 0, 1, 2 | |
| DISPATCH_STALL_FOR_SERIALIZATION | Microsequencer Stall due to Serialization | 0, 1, 2 | |
| DISPATCH_STALL_FOR_RETIRE_QUEUE_FULL | Dispatch Stall for Instruction Retire Q Full | 0, 1, 2 | |
| DISPATCH_STALL_FOR_INT_SCHED_QUEUE_FULL | Dispatch Stall for Integer Scheduler Queue Full | 0, 1, 2 | |
| DISPATCH_STALL_FOR_FPU_FULL | Dispatch Stall for FP Scheduler Queue Full | 0, 1, 2 | |
| DISPATCH_STALL_FOR_LDQ_FULL | Dispatch Stall for LDQ Full | 0, 1, 2 | |
| MICROSEQ_STALL_WAITING_FOR_ALL_QUIET | Microsequencer Stall Waiting for All Quiet | 0, 1, 2 | |
| FPU_EXCEPTIONS | FPU Exceptions | all |
0x01: Total microfaults
0x02: Total microtraps 0x04: Int2Ext faults 0x08: Ext2Int faults 0x10: Bypass faults |
| DR0_BREAKPOINTS | DR0 Breakpoint Match | all | |
| DR1_BREAKPOINTS | DR1 Breakpoint Match | all | |
| DR2_BREAKPOINTS | DR2 Breakpoint Match | all | |
| DR3_BREAKPOINTS | DR3 Breakpoint Match | all | |
| IBS_OPS_TAGGED | Tagged IBS Ops | all |
0x01: Number of ops tagged by IBS
0x02: Number of ops tagged by IBS that retired 0x04: Number of times op could not be tagged by IBS because of previous tagged op that has not retired |
| DISPATCH_STALL_FOR_STQ_FULL | Dispatch Stall for STQ Full | all |
It is a capital mistake to theorise before one has data. Insensibly one begins to twist facts to suit theories instead of theories to suit facts.- Sherlock Holmes