AMD family 12h events

This is a list of AMD64 family 12h's CPU's performance counter event types. Please see BIOS and Kernel Developer's Guide for AMD Family 12h Processors.

Name	Description	Counters usable	Unit mask options
DISPATCHED_FPU_OPS	Dispatched FPU Operations	all	0x01: Add pipe ops excluding load ops and SSE move ops 0x02: Multiply pipe ops excluding load ops and SSE move ops 0x04: Store pipe ops excluding load ops and SSE move ops 0x08: Add pipe load ops and SSE move ops 0x10: Multiply pipe load ops and SSE move ops 0x20: Store pipe load ops and SSE move ops 0x3f: All ops
CYCLES_FPU_EMPTY	Cycles in which the FPU is Empty	all
DISPATCHED_FPU_OPS_FAST_FLAG	Dispatched Fast Flag FPU Operations	all
RETIRED_SSE_OPS	Retired SSE Operations	all	0x01: Single Precision add/subtract ops 0x02: Single precision multiply ops 0x04: Single precision divide/square root ops 0x08: Double precision add/subtract ops 0x10: Double precision multiply ops 0x20: Double precision divide/square root ops 0x40: OP type: 0=uops 1=FLOPS
RETIRED_MOVE_OPS	Retired Move Ops	all	0x01: Merging low quadword move uops 0x02: Merging high quadword move uops 0x04: All other merging move uops 0x08: All other move uops
RETIRED_SERIALIZING_OPS	Retired Serializing Ops	all	0x01: SSE bottom-executing uops retired 0x02: SSE bottom-serializing uops retired 0x04: x87 bottom-executing uops retired 0x08: x87 bottom-serializing uops retired
SERIAL_UOPS_IN_FP_SCHED	Number of Cycles that a Serializing uop is in the FP Scheduler	all	0x01: Number of cycles a bottom-execute uops in FP scheduler 0x02: Number of cycles a bottom-serializing uops in FP scheduler
SEGMENT_REGISTER_LOADS	Segment Register Loads	all	0x01: ES register 0x02: CS register 0x04: SS register 0x08: DS register 0x10: FS register 0x20: GS register 0x40: HS register
PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE	Pipeline Restart Due to Self-Modifying Code	all
PIPELINE_RESTART_DUE_TO_PROBE_HIT	Pipeline Restart Due to Probe Hit	all
LS_BUFFER_2_FULL_CYCLES	LS Buffer 2 Full	all
LOCKED_OPS	Locked Operations	all	0x01: Number of locked instructions executed 0x02: Cycles in speculative phase 0x04: Cycles in non-speculative phase (including cache miss penalty) 0x08: Cache miss penalty in cycles
RETIRED_CLFLUSH_INSTRUCTIONS	Retired CLFLUSH Instructions	all
RETIRED_CPUID_INSTRUCTIONS	Retired CPUID Instructions	all
CANCELLED_STORE_TO_LOAD	Cancelled Store to Load Forward Operations	all	0x01: Address mismatches (starting byte not the same) 0x02: Store is smaller than load 0x04: Misaligned
SMIS_RECEIVED	SMIs Received	all
DATA_CACHE_ACCESSES	Data Cache Accesses	all
DATA_CACHE_MISSES	Data Cache Misses	all
DATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGE	Data Cache Refills from L2 or Northbridge	all	0x01: Refill from northbridge 0x02: Shared-state line from L2 0x04: Exclusive-state line from L2 0x08: Owner-state line from L2 0x10: Modified-state line from L2 0x1e: All cache states except refill from northbridge
DATA_CACHE_REFILLS_FROM_NORTHBRIDGE	Data Cache Refills from the Northbridge	all	0x01: (I)nvalid cache state 0x02: (S)hared cache state 0x04: (E)xclusive cache state 0x08: (O)wned cache state 0x10: (M)odified cache state 0x1f: All cache states
DATA_CACHE_LINES_EVICTED	Data Cache Lines Evicted	all	0x01: (I)nvalid cache state 0x02: (S)hared cache state 0x04: (E)xclusive cache state 0x08: (O)wned cache state 0x10: (M)odified cache state 0x20: Cache line evicted brought into the cache by PrefetchNTA 0x40: Cache line evicted not brought into the cache by PrefetchNTA
L1_DTLB_MISS_AND_L2_DTLB_HIT	L1 DTLB Miss and L2 DTLB Hit	all	0x01: L2 4K TLB hit 0x02: L2 2M TLB hit 0x04: L2 1G TLB hit
L1_DTLB_AND_L2_DTLB_MISS	L1 DTLB and L2 DTLB Miss	all	0x01: 4K TLB reload 0x02: 2M TLB reload 0x04: 1G TLB reload
MISALIGNED_ACCESSES	Misaligned Accesses	all
MICRO_ARCH_LATE_CANCEL_ACCESS	Microarchitectural Late Cancel of an Access	all
MICRO_ARCH_EARLY_CANCEL_ACCESS	Microarchitectural Early Cancel of an Access	all
PREFETCH_INSTRUCTIONS_DISPATCHED	Prefetch Instructions Dispatched	all	0x01: Load (Prefetch, PrefetchT0/T1/T2) 0x02: Store (PrefetchW) 0x04: NTA (PrefetchNTA)
LOCKED_INSTRUCTIONS_DCACHE_MISSES	DCACHE Misses by Locked Instructions	all	0x02: Data cache misses by locked instructions
L1_DTLB_HIT	L1 DTLB Hit	all	0x01: L1 4K TLB hit 0x02: L1 2M TLB hit 0x04: L1 1G TLB hit
INEFFECTIVE_SW_PREFETCHES	Ineffective Software Prefetches	all	0x01: Software prefetch hit in L1 0x08: Software prefetch hit in L2
GLOBAL_TLB_FLUSHES	Global TLB Flushes	all
MEMORY_REQUESTS	Memory Requests by Type	all	0x01: Requests to non-cacheable (UC) memory 0x02: Requests to write-combining (WC) memory or WC buffer flushes to WB memory 0x04: Requests to cache-disabled (CD) memory 0x80: Streaming store (SS) requests
DATA_PREFETCHES	Data Prefetcher	all	0x01: Cancelled prefetches 0x02: Prefetch attempts
NORTHBRIDGE_READ_RESPONSES	Northbridge Read Responses by Coherency State	all	0x01: Exclusive 0x02: Modified 0x04: Shared 0x08: Owned 0x10: Data Error
OCTWORD_WRITE_TRANSFERS	Octwords Written to System	all	0x01: Octword write transfer
CPU_CLK_UNHALTED	CPU Clocks not Halted	all
REQUESTS_TO_L2	Requests to L2 Cache	all	0x01: IC fill 0x02: DC fill 0x04: TLB fill (page table walks) 0x08: Tag snoop request 0x10: Canceled request 0x20: Hardware prefetch from data cache
L2_CACHE_MISS	L2 Cache Misses	all	0x01: IC fill 0x02: DC fill (includes possible replays) 0x04: TLB page table walk 0x08: Hardware prefetch from data cache
L2_CACHE_FILL_WRITEBACK	L2 Fill/Writeback	all	0x01: L2 fills (victims from L1 caches, TLB page table walks and data prefetches) 0x02: L2 writebacks to system
PAGE_SIZE_MISMATCHES	Page Size Mismatches	all	0x01: Guest page size is larger than the host page size 0x02: MTRR mismatch 0x04: Host page size is larger than the guest page size
INSTRUCTION_CACHE_FETCHES	Instruction Cache Fetches	all
INSTRUCTION_CACHE_MISSES	Instruction Cache Misses	all
INSTRUCTION_CACHE_REFILLS_FROM_L2	Instruction Cache Refills from L2	all
INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM	Instruction Cache Refills from System	all
L1_ITLB_MISS_AND_L2_ITLB_HIT	L1 ITLB Miss, L2 ITLB Hit	all
L1_ITLB_MISS_AND_L2_ITLB_MISS	L1 ITLB Miss, L2 ITLB Miss	all	0x01: Instruction fetches to a 4K page 0x02: Instruction fetches to a 2M page
PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE	Pipeline Restart Due to Instruction Stream Probe	all
INSTRUCTION_FETCH_STALL	Instruction Fetch Stall	all
RETURN_STACK_HITS	Return Stack Hits	all
RETURN_STACK_OVERFLOWS	Return Stack Overflows	all
INSTRUCTION_CACHE_VICTIMS	Instruction Cache Victims	all
INSTRUCTION_CACHE_INVALIDATED	Instruction Cache Lines Invalidated	all	0x01: Invalidating probe that did not hit any in-flight instructions 0x02: Invalidating probe that hit one or more in-flight instructions 0x04: SMC that did not hit any in-flight instructions 0x08: SMC that hit one or more in-flight instructions
ITLB_RELOADS	ITLB Reloads	all
ITLB_RELOADS_ABORTED	ITLB Reloads Aborted	all
RETIRED_INSTRUCTIONS	Retired Instructions	all
RETIRED_UOPS	Retired uops	all
RETIRED_BRANCH_INSTRUCTIONS	Retired Branch Instructions	all
RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS	Retired Mispredicted Branch Instructions	all
RETIRED_TAKEN_BRANCH_INSTRUCTIONS	Retired Taken Branch Instructions	all
RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED	Retired Taken Branch Instructions Mispredicted	all
RETIRED_FAR_CONTROL_TRANSFERS	Retired Far Control Transfers	all
RETIRED_BRANCH_RESYNCS	Retired Branch Resyncs	all
RETIRED_NEAR_RETURNS	Retired Near Returns	all
RETIRED_NEAR_RETURNS_MISPREDICTED	Retired Near Returns Mispredicted	all
RETIRED_INDIRECT_BRANCHES_MISPREDICTED	Retired Indirect Branches Mispredicted	all
RETIRED_MMX_FP_INSTRUCTIONS	Retired MMX(tm)/FP Instructions	all	0x01: x87 instructions 0x02: MMX & 3DNow instructions 0x04: SSE instructions (SSE, SSE2, SSE3, and SSE4A)
INTERRUPTS_MASKED_CYCLES	Interrupts-Masked Cycles	all
INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING	Interrupts-Masked Cycles with Interrupt Pending	all
INTERRUPTS_TAKEN	Interrupts Taken	all
DECODER_EMPTY	Decoder Empty	all
DISPATCH_STALLS	Dispatch Stalls	all
DISPATCH_STALL_FOR_BRANCH_ABORT	Dispatch Stall for Branch Abort to Retire	all
DISPATCH_STALL_FOR_SERIALIZATION	Dispatch Stall for Serialization	all
DISPATCH_STALL_FOR_SEGMENT_LOAD	Dispatch Stall for Segment Load	all
DISPATCH_STALL_FOR_REORDER_BUFFER_FULL	Dispatch Stall for Reorder Buffer Full	all
DISPATCH_STALL_FOR_RESERVATION_STATION_FULL	Dispatch Stall for Reservation Station Full	all
DISPATCH_STALL_FOR_FPU_FULL	Dispatch Stall for FPU Full	all
DISPATCH_STALL_FOR_LS_FULL	Dispatch Stall for LS Full	all
DISPATCH_STALL_WAITING_FOR_ALL_QUIET	Dispatch Stall Waiting for All Quiet	all
DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RESYNC	Dispatch Stall for Far Transfer or Resync to Retire	all
FPU_EXCEPTIONS	FPU Exceptions	all	0x01: x87 reclass microfaults 0x02: SSE retype microfaults 0x04: SSE reclass microfaults 0x08: SSE and x87 microtraps
DR0_BREAKPOINTS	DR0 Breakpoint Matches	all
DR1_BREAKPOINTS	DR1 Breakpoint Matches	all
DR2_BREAKPOINTS	DR2 Breakpoint Matches	all
DR3_BREAKPOINTS	DR3 Breakpoint Matches	all
RETIRED_X87_FLOATING_POINT_OPERATIONS	Retired x87 Floating Point Operations	all	0x01: Add/subtract ops 0x02: Multiply ops 0x04: Divide ops
LFENCE_INSTRUCTIONS_RETIRED	LFENCE Instructions Retired	all
SFENCE_INSTRUCTIONS_RETIRED	SFENCE Instructions Retired	all
MFENCE_INSTRUCTIONS_RETIRED	MFENCE Instructions Retired	all
DRAM_ACCESSES	DRAM Accesses	all	0x01: DCT0 Page hit 0x02: DCT0 Page miss 0x04: DCT0 Page conflict 0x08: DCT1 Page hit 0x10: DCT1 Page miss 0x20: DCT1 Page Conflict 0x40: Write request 0x80: Read request
DCT0_PAGE_TABLE_EVENTS	DRAM Controller 0 Page Table Events	all	0x01: DCT0 Page Table Overflow 0x02: DCT0 Number of stale table entry hits 0x04: DCT0 Page table idle cycle limit incremented 0x08: DCT0 Page table idle cycle limit decremented 0x10: DCT0 Page table is closed due to row inactivity
MEMORY_CONTROLLER_SLOT_MISSED	Memory Controller DRAM Command Slots Missed	all	0x10: DCT0 RBD 0x20: DCT1 RBD 0x40: DCT0 Prefetch 0x80: DCT1 Prefetch
MEMORY_CONTROLLER_TURNAROUNDS	Memory Controller Turnarounds	all	0x01: DCT0 read-to-write turnaround 0x02: DCT0 write-to-read turnaround 0x08: DCT1 read-to-write turnaround 0x10: DCT1 write-to-read turnaround
MEMORY_CONTROLLER_RBD_QUEUE_EVENTS	Memory Controller RBD Queue Events	all	0x04: D18F2x[1,0]94[DcqBypassMax] counter reached 0x08: Bank is closed due to bank conflict with an outstanding request in the RBD queue
DCT1_PAGE_TABLE_EVENTS	DRAM Controller 1 Page Table Events	all	0x01: DCT1 Page Table Overflow 0x02: DCT1 Number of stale table entry hits 0x04: DCT1 Page table idle cycle limit incremented 0x08: DCT1 Page table idle cycle limit decremented 0x10: DCT1 Page table is closed due to row inactivity
THERMAL_STATUS	Thermal Status	all	0x01: MEMHOT_L assertions 0x04: Number of times the HTC transitions from inactive to active 0x20: Number of clocks HTC P-state is inactive 0x40: Number of clocks HTC P-state is active 0x80: PROCHOT_L asserted by external source and caused a P-state change
CPU_IO_REQUESTS_TO_MEMORY_IO	CPU/IO Requests to Memory/IO	all	0x01: IO to IO 0x02: IO to Mem 0x04: CPU to IO 0x08: CPU to Mem
CACHE_BLOCK_COMMANDS	Cache Block Commands	all	0x01: Victim Block (Writeback) 0x04: Read Block (Dcache load miss refill) 0x08: Read Block Shared (Icache refill) 0x10: Read Block Modified (Dcache store miss refill) 0x20: Change-to-Dirty (first store to clean block already in cache)
SIZED_COMMANDS	Sized Commands	all	0x01: Non-posted write byte (1-32 bytes) 0x02: Non-posted write DWORD (1-16 DWORDs) 0x04: Posted write byte (1-32 bytes) 0x08: Posted write DWORD (1-16 DWORDs) 0x10: Read byte (4 bytes) 0x20: Read DWORD (1-16 DWORDs)
PROBE_RESPONSES_AND_UPSTREAM_REQUESTS	Probe Responses and Upstream Requests	all	0x01: Probe miss 0x02: Probe hit clean 0x04: Probe hit dirty without memory cancel 0x08: Probe hit dirty with memory cancel 0x10: Upstream high priority reads 0x20: Upstream low priority reads 0x80: Upstream low priority writes
DEV_EVENTS	DEV Events	all	0x10: DEV hit 0x20: DEV miss 0x40: DEV error
MEMORY_CONTROLLER_REQUESTS	Memory Controller Requests	all	0x01: Write requests 0x02: Read Requests 0x04: Prefetch Requests 0x08: 32 Bytes Sized Writes 0x10: 64 Bytes Sized Writes 0x20: 32 Bytes Sized Reads 0x40: 64 Byte Sized Reads 0x80: Read requests while writes pending in DCQ
SIDEBAND_SIGNALS	Sideband Signals and Special Cycles	all	0x02: STOPGRANT 0x04: SHUTDOWN 0x08: WBINVD 0x10: INVD
INTERRUPT_EVENTS	Interrupt Events	all	0x01: Fixed and LPA 0x02: LPA 0x04: SMI 0x08: NMI 0x10: INIT 0x20: STARTUP 0x40: INT 0x80: EOI