This is a list of AMD64 family 10's CPU's performance counter event types. Please see the AMD Optimization Manual for more details. Note that any counter can be used for any event.
| Name | Description | Counters usable | Unit mask options |
| DISPATCHED_FPU_OPS | Dispatched FPU ops | all |
0x01: Add pipe ops excluding load ops and SSE move ops
0x02: Multiply pipe ops excluding load ops and SSE move ops 0x04: Store pipe ops excluding load ops and SSE move ops 0x08: Add pipe load ops and SSE move ops 0x10: Multiply pipe load ops and SSE move ops 0x20: Store pipe load ops and SSE move ops 0x3f: All ops |
| CYCLES_FPU_EMPTY | The number of cycles in which the PFU is empty | all | |
| DISPATCHED_FPU_OPS_FAST_FLAG | The number of FPU operations that use the fast flag interface | all | |
| RETIRED_SSE_OPS | The number of SSE ops or uops retired | all |
0x01: Single Precision add/subtract ops
0x02: Single precision multiply ops 0x04: Single precision divide/square root ops 0x08: Double precision add/subtract ops 0x10: Double precision multiply ops 0x20: Double precision divide/square root ops 0x40: OP type: 0=uops 1=FLOPS |
| RETIRED_MOVE_OPS | The number of move uops retired | all |
0x01: Merging low quadword move uops
0x02: Merging high quadword move uops 0x04: All other merging move uops 0x08: All other move uops |
| RETIRED_SERIALIZING_OPS | The number of serializing uops retired. | all |
0x01: SSE bottom-executing uops retired
0x02: SSE bottom-serializing uops retired 0x04: x87 bottom-executing uops retired 0x08: x87 bottom-serializing uops retired |
| SERIAL_UOPS_IN_FP_SCHED | Number of cycles a serializing uop is in the FP scheduler | all |
0x01: Number of cycles a bottom-execute uops in FP scheduler
0x02: Number of cycles a bottom-serializing uops in FP scheduler |
| SEGMENT_REGISTER_LOADS | Segment register loads | all |
0x01: ES register
0x02: CS register 0x04: SS register 0x08: DS register 0x10: FS register 0x20: GS register 0x40: HS register |
| PIPELINE_RESTART_DUE_TO_SELF_MODIFYING_CODE | Micro-architectural re-sync caused by self modifying code | all | |
| PIPELINE_RESTART_DUE_TO_PROBE_HIT | Micro-architectural re-sync caused by snoop | all | |
| LS_BUFFER_2_FULL_CYCLES | Cycles LS Buffer 2 Full | all | |
| LOCKED_OPS | Locked operations | all |
0x01: Number of locked instructions executed
0x02: Cycles in speculative phase 0x04: Cycles in non-speculative phase (including cache miss penalty) 0x08: Cache miss penalty in cycles |
| RETIRED_CLFLUSH_INSTRUCTIONS | Retired CLFLUSH instructions | all | |
| RETIRED_CPUID_INSTRUCTIONS | Retired CPUID instructions | all | |
| CANCELLED_STORE_TO_LOAD | Counts the number of cancelled store to load forward operations | all |
0x01: Address mismatches (starting byte not the same)
0x02: Store is smaller than load 0x04: Misaligned |
| SMIS_RECEIVED | Counts the number of SMIs received by the processor | all | |
| DATA_CACHE_ACCESSES | Data cache accesses | all | |
| DATA_CACHE_MISSES | Data cache misses | all | |
| DATA_CACHE_REFILLS_FROM_L2_OR_NORTHBRIDGE | Data cache refills from L2 or Northbridge | all |
0x01: Refill from northbridge
0x02: Shared-state line from L2 0x04: Exclusive-state line from L2 0x08: Owner-state line from L2 0x10: Modified-state line from L2 0x1e: All cache states except refill from northbridge |
| DATA_CACHE_REFILLS_FROM_NORTHBRIDGE | Data cache refills from Northbridge | all |
0x01: (I)nvalid cache state
0x02: (S)hared cache state 0x04: (E)xclusive cache state 0x08: (O)wner cache state 0x10: (M)odified cache state 0x1f: All cache states |
| DATA_CACHE_LINES_EVICTED | Data cache lines evicted | all |
0x01: (I)nvalid cache state
0x02: (S)hared cache state 0x04: (E)xclusive cache state 0x08: (O)wner cache state 0x10: (M)odified cache state 0x20: Cache line evicted brought into the cache by PrefetchNTA 0x40: Cache line evicted not brought into the cache by PrefetchNTA |
| L1_DTLB_MISS_AND_L2_DTLB_HIT | L1 DTLB miss and L2 DTLB hit | all |
0x01: L2 4K TLB hit
0x02: L2 2M TLB hit 0x04: L2 1G TLB hit (RevC) |
| L1_DTLB_AND_L2_DTLB_MISS | L1 DTLB and L2 DTLB miss | all |
0x01: 4K TLB reload
0x02: 2M TLB reload 0x04: 1G TLB reload |
| MISALIGNED_ACCESSES | Misaligned Accesses | all | |
| MICRO_ARCH_LATE_CANCEL_ACCESS | Microarchitectural late cancel of an access | all | |
| MICRO_ARCH_EARLY_CANCEL_ACCESS | Microarchitectural early cancel of an access | all | |
| 1_BIT_ECC_ERRORS | Single-bit ECC errors recorded by scrubber | all |
0x01: Scrubber error
0x02: Piggyback scrubber errors 0x04: Load pipe error 0x08: Store write pip error |
| PREFETCH_INSTRUCTIONS_DISPATCHED | The number of prefetch instructions dispatched by the decoder | all |
0x01: Load (Prefetch, PrefetchT0/T1/T2)
0x02: Store (PrefetchW) 0x04: NTA (PrefetchNTA) |
| LOCKED_INSTRUCTIONS_DCACHE_MISSES | The number of dta cache misses by locked instructions. | all |
0x02: Data cache misses by locked instructions
|
| L1_DTLB_HIT | L1 DTLB hit | all |
0x01: L1 4K TLB hit
0x02: L1 2M TLB hit 0x04: L1 1G TLB hit |
| INEFFECTIVE_SW_PREFETCHES | Number of software prefetches that did not fetch data outside of processor core | all |
0x01: Software prefetch hit in L1
0x08: Software prefetch hit in L2 |
| GLOBAL_TLB_FLUSHES | The number of global TLB flushes | all | |
| MEMORY_REQUESTS | Memory requests by type | all |
0x01: Requests to non-cacheable (UC) memory
0x02: Requests to write-combining (WC) memory or WC buffer flushes to WB memory 0x80: Streaming store (SS) requests |
| DATA_PREFETCHES | Data prefetcher | all |
0x01: Cancelled prefetches
0x02: Prefetch attempts |
| MAB_REQS | MAB Requests | all |
0x00: DC miss buffer 0
0x01: DC miss buffer 1 0x02: DC miss buffer 2 0x03: DC miss buffer 3 0x04: DC miss buffer 4 0x05: DC miss buffer 5 0x06: DC miss buffer 6 0x07: DC miss buffer 7 0x08: IC miss buffer 0 0x09: IC miss buffer 1 |
| MAB_WAIT | MAB Wait Cycles | all |
0x00: DC miss buffer 0
0x01: DC miss buffer 1 0x02: DC miss buffer 2 0x03: DC miss buffer 3 0x04: DC miss buffer 4 0x05: DC miss buffer 5 0x06: DC miss buffer 6 0x07: DC miss buffer 7 0x08: IC miss buffer 0 0x09: IC miss buffer 1 |
| NORTHBRIDGE_READ_RESPONSES | Northbridge read responses by coherency state | all |
0x01: Exclusive
0x02: Modified 0x04: Shared 0x08: Owned 0x10: Data Error |
| OCTWORD_WRITE_TRANSFERS | Octwords written to system | all |
0x01: Octword write transfer
|
| CPU_CLK_UNHALTED | Cycles outside of halt state | all | |
| REQUESTS_TO_L2 | Requests to L2 Cache | all |
0x01: IC fill
0x02: DC fill 0x04: TLB fill (page table walks) 0x08: Tag snoop request 0x10: Canceled request 0x20: Hardware prefetch from data cache |
| L2_CACHE_MISS | L2 cache misses | all |
0x01: IC fill
0x02: DC fill (includes possible replays) 0x04: TLB page table walk 0x08: Hardware prefetch from data cache |
| L2_CACHE_FILL_WRITEBACK | L2 fill/writeback | all |
0x01: L2 fills (victims from L1 caches, TLB page table walks and data prefetches)
0x02: L2 writebacks to system |
| PAGE_SIZE_MISMATCHES | Page Size Mismatches | all |
0x01: Guest page size is larger than the host page size
0x02: MTRR mismatch 0x04: Host page size is larger than the guest page size |
| INSTRUCTION_CACHE_FETCHES | Instruction cache fetches (RevE) | all | |
| INSTRUCTION_CACHE_MISSES | Instruction cache misses | all | |
| INSTRUCTION_CACHE_REFILLS_FROM_L2 | Instruction cache refills from L2 | all | |
| INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM | Instruction cache refills from system | all | |
| L1_ITLB_MISS_AND_L2_ITLB_HIT | L1 ITLB miss and L2 ITLB hit | all | |
| L1_ITLB_MISS_AND_L2_ITLB_MISS | L1 ITLB miss and L2 ITLB miss | all |
0x01: Instruction fetches to a 4K page
0x02: Instruction fetches to a 2M page |
| PIPELINE_RESTART_DUE_TO_INSTRUCTION_STREAM_PROBE | Pipeline restart due to instruction stream probe | all | |
| INSTRUCTION_FETCH_STALL | Instruction fetch stall | all | |
| RETURN_STACK_HITS | Return stack hit | all | |
| RETURN_STACK_OVERFLOWS | Return stack overflow | all | |
| INSTRUCTION_CACHE_VICTIMS | Number of instruction cache lines evicticed to the L2 cache | all | |
| INSTRUCTION_CACHE_INVALIDATED | Instruction cache lines invalidated | all |
0x01: Invalidating probe that did not hit any in-flight instructions
0x02: Invalidating probe that hit one or more in-flight instructions |
| ITLB_RELOADS | The number of ITLB reloads requests | all | |
| ITLB_RELOADS_ABORTED | The number of ITLB reloads aborted | all | |
| RETIRED_INSTRUCTIONS | Retired instructions (includes exceptions, interrupts, re-syncs) | all | |
| RETIRED_UOPS | Retired micro-ops | all | |
| RETIRED_BRANCH_INSTRUCTIONS | Retired branches (conditional, unconditional, exceptions, interrupts) | all | |
| RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS | Retired mispredicted branch instructions | all | |
| RETIRED_TAKEN_BRANCH_INSTRUCTIONS | Retired taken branch instructions | all | |
| RETIRED_TAKEN_BRANCH_INSTRUCTIONS_MISPREDICTED | Retired taken branches mispredicted | all | |
| RETIRED_FAR_CONTROL_TRANSFERS | Retired far control transfers | all | |
| RETIRED_BRANCH_RESYNCS | Retired branches resyncs (only non-control transfer branches) | all | |
| RETIRED_NEAR_RETURNS | Retired near returns | all | |
| RETIRED_NEAR_RETURNS_MISPREDICTED | Retired near returns mispredicted | all | |
| RETIRED_INDIRECT_BRANCHES_MISPREDICTED | Retired indirect branches mispredicted | all | |
| RETIRED_MMX_FP_INSTRUCTIONS | Retired MMX/FP instructions | all |
0x01: x87 instructions
0x02: MMX & 3DNow instructions 0x04: SSE instructions (SSE, SSE2, SSE3, and SSE4A) |
| RETIRED_FASTPATH_DOUBLE_OP_INSTRUCTIONS | Retired FastPath double-op instructions | all |
0x01: With low op in position 0
0x02: With low op in position 1 0x04: With low op in position 2 |
| INTERRUPTS_MASKED_CYCLES | Cycles with interrupts masked (IF=0) | all | |
| INTERRUPTS_MASKED_CYCLES_WITH_INTERRUPT_PENDING | Cycles with interrupts masked while interrupt pending | all | |
| INTERRUPTS_TAKEN | Number of taken hardware interrupts | all | |
| DECODER_EMPTY | Nothing to dispatch (decoder empty) | all | |
| DISPATCH_STALLS | Dispatch stalls | all | |
| DISPATCH_STALL_FOR_BRANCH_ABORT | Dispatch stall from branch abort to retire | all | |
| DISPATCH_STALL_FOR_SERIALIZATION | Dispatch stall for serialization | all | |
| DISPATCH_STALL_FOR_SEGMENT_LOAD | Dispatch stall for segment load | all | |
| DISPATCH_STALL_FOR_REORDER_BUFFER_FULL | Dispatch stall for reorder buffer full | all | |
| DISPATCH_STALL_FOR_RESERVATION_STATION_FULL | Dispatch stall when reservation stations are full | all | |
| DISPATCH_STALL_FOR_FPU_FULL | Dispatch stall when FPU is full | all | |
| DISPATCH_STALL_FOR_LS_FULL | Dispatch stall when LS is full | all | |
| DISPATCH_STALL_WAITING_FOR_ALL_QUIET | Dispatch stall when waiting for all to be quiet | all | |
| DISPATCH_STALL_FOR_FAR_TRANSFER_OR_RESYNC | Dispatch Stall for Far Transfer or Resync to Retire | all | |
| FPU_EXCEPTIONS | FPU exceptions | all |
0x01: x87 reclass microfaults
0x02: SSE retype microfaults 0x04: SSE reclass microfaults 0x08: SSE and x87 microtraps |
| DR0_BREAKPOINTS | The number of matches on the address in breakpoint register DR0 | all | |
| DR1_BREAKPOINTS | The number of matches on the address in breakpoint register DR1 | all | |
| DR2_BREAKPOINTS | The number of matches on the address in breakpoint register DR2 | all | |
| DR3_BREAKPOINTS | The number of matches on the address in breakpoint register DR3 | all | |
| RETIRED_X87_FLOATING_POINT_OPERATIONS | Retired x87 Floating Point Operations (RevC and later) | all |
0x01: Add/subtract ops
0x02: Multiply ops 0x04: Divide ops |
| IBS_OPS_TAGGED | IBS Ops Tagged (RevC and later) | all | |
| LFENCE_INSTRUCTIONS_RETIRED | LFENCE Instructions Retired (RevC and later) | all | |
| SFENCE_INSTRUCTIONS_RETIRED | SFENCE Instructions Retired (RevC and later) | all | |
| MFENCE_INSTRUCTIONS_RETIRED | MFENCE Instructions Retired (RevC and later) | all | |
| DRAM_ACCESSES | DRAM accesses | all |
0x01: DCT0 Page hit
0x02: DCT0 Page miss 0x04: DCT0 Page conflict 0x08: DCT1 Page hit 0x10: DCT1 Page miss 0x20: DCT1 Page Conflict |
| MEMORY_CONTROLLER_PAGE_TABLE_OVERFLOWS | Memory controller page table overflows | all |
0x01: DCT0 Page Table Overflow
0x02: DCT1 Page Table Overflow |
| MEMORY_CONTROLLER_SLOT_MISSED | Memory controller DRAM command slots missed | all |
0x01: DCT0 Command slots missed
0x02: DCT2 Command slots missed |
| MEMORY_CONTROLLER_TURNAROUNDS | Memory controller turnarounds | all |
0x01: DCT0 DIMM (chip select) turnaround
0x02: DCT0 Read to write turnaround 0x04: DCT0 Write to read turnaround 0x08: DCT1 DIMM (chip select) turnaround 0x10: DCT1 Read to write turnaround 0x20: DCT1 Write to read turnaround |
| MEMORY_CONTROLLER_BYPASS_COUNTER_SATURATION | Memory controller bypass saturation | all |
0x01: Memory controller high priority bypass
0x02: Memory controller medium priority bypass 0x04: DCT0 DCQ bypass 0x08: DCT1 DCQ bypass |
| THERMAL_STATUS | Thermal status | all |
0x04: Number of times the HTC trip point is crossed
0x08: Number of clocks when STC trip point active 0x10: Number of times the STC trip point is crossed 0x20: Number of clocks HTC P-state is inactive 0x40: Number of clocks HTC P-state is active |
| CPU_IO_REQUESTS_TO_MEMORY_IO | CPU/IO Requests to Memory/IO | all |
0xa1: Requests Local I/O to Local I/O
0xa2: Requests Local I/O to Local Memory 0xa3: Requests Local I/O to Local (I/O or Mem) 0xa4: Requests Local CPU to Local I/O 0xa5: Requests Local (CPU or I/O) to Local I/O 0xa8: Requests Local CPU to Local Memory 0xaa: Requests Local (CPU or I/O) to Local Memory 0xac: Requests Local CPU to Local (I/O or Mem) 0xaf: Requests Local (CPU or I/O) to Local (I/O or Mem) 0x91: Requests Local I/O to Remote I/O 0x92: Requests Local I/O to Remote Memory 0x93: Requests Local I/O to Remote (I/O or Mem) 0x94: Requests Local CPU to Remote I/O 0x95: Requests Local (CPU or I/O) to Remote I/O 0x98: Requests Local CPU to Remote Memory 0x9a: Requests Local (CPU or I/O) to Remote Memory 0x9c: Requests Local CPU to Remote (I/O or Mem) 0x9f: Requests Local (CPU or I/O) to Remote (I/O or Mem) 0xb1: Requests Local I/O to Any I/O 0xb2: Requests Local I/O to Any Memory 0xb3: Requests Local I/O to Any (I/O or Mem) 0xb4: Requests Local CPU to Any I/O 0xb5: Requests Local (CPU or I/O) to Any I/O 0xb8: Requests Local CPU to Any Memory 0xba: Requests Local (CPU or I/O) to Any Memory 0xbc: Requests Local CPU to Any (I/O or Mem) 0xbf: Requests Local (CPU or I/O) to Any (I/O or Mem) 0x61: Requests Remote I/O to Local I/O 0x64: Requests Remote CPU to Local I/O 0x65: Requests Remote (CPU or I/O) to Local I/O |
| CACHE_BLOCK_COMMANDS | Cache block commands | all |
0x01: Victim Block (Writeback)
0x04: Read Block (Dcache load miss refill) 0x08: Read Block Shared (Icache refill) 0x10: Read Block Modified (Dcache store miss refill) 0x20: Change-to-Dirty (first store to clean block already in cache) |
| SIZED_COMMANDS | Sized commands | all |
0x01: Non-posted write byte (1-32 bytes)
0x02: Non-posted write DWORD (1-16 DWORDs) 0x04: Posted write byte (1-32 bytes) 0x08: Posted write DWORD (1-16 DWORDs) 0x10: Read byte (4 bytes) 0x20: Read DWORD (1-16 DWORDs) |
| PROBE_RESPONSES_AND_UPSTREAM_REQUESTS | Probe responses and upstream requests | all |
0x01: Probe miss
0x02: Probe hit clean 0x04: Probe hit dirty without memory cancel 0x08: Probe hit dirty with memory cancel 0x10: Upstream display refresh/ISOC reads 0x20: Upstream non-display refresh reads 0x40: Upstream ISOC writes 0x80: Upstream non-ISOC writes |
| GART_EVENTS | GART events | all |
0x01: GART aperture hit on access from CPU
0x02: GART aperture hit on access from I/O 0x04: GART miss 0x08: GART/DEV request hit table walk in progress 0x10: DEV hit 0x20: DEV miss 0x40: DEV error 0x80: GART/DEV multiple table walk in progress |
| MEMORY_CONTROLLER_REQUESTS | Sized read/write activity. | all |
0x01: Write requests
0x02: Read Requests including Prefetch 0x04: Prefetch Request 0x08: 32 Bytes Sized Writes 0x10: 64 Bytes Sized Writes 0x20: 32 Bytes Sized Reads 0x40: 64 Byte Sized Reads 0x80: Read requests sent to the DCT while write requests are pending in the DCQ |
| CPU_DRAM_REQUEST_TO_NODE | CPU to DRAM requests to target node | all |
0x01: From local node to node 0
0x02: From local node to node 1 0x04: From local node to node 2 0x08: From local node to node 3 0x10: From local node to node 4 0x20: From local node to node 5 0x40: From local node to node 6 0x80: From local node to node 7 |
| IO_DRAM_REQUEST_TO_NODE | IO to DRAM requests to target node | all |
0x01: From local node to node 0
0x02: From local node to node 1 0x04: From local node to node 2 0x08: From local node to node 3 0x10: From local node to node 4 0x20: From local node to node 5 0x40: From local node to node 6 0x80: From local node to node 7 |
| CPU_READ_COMMAND_LATENCY_NODE_0_3 | Latency between the local node and remote node | all |
0x01: Read block
0x02: Read block shared 0x04: Read block modified 0x08: Change-to-Dirty 0x10: From local node to node 0 0x20: From local node to node 1 0x40: From local node to node 2 0x80: From local node to node 3 |
| CPU_READ_COMMAND_REQUEST_NODE_0_3 | Number of requests that a latency measurement is made for Event 0x1E2 | all |
0x01: Read block
0x02: Read block shared 0x04: Read block modified 0x08: Change-to-Dirty 0x10: From local node to node 0 0x20: From local node to node 1 0x40: From local node to node 2 0x80: From local node to node 3 |
| CPU_READ_COMMAND_LATENCY_NODE_4_7 | Latency between the local node and remote node | all |
0x01: Read block
0x02: Read block shared 0x04: Read block modified 0x08: Change-to-Dirty 0x10: From local node to node 4 0x20: From local node to node 5 0x40: From local node to node 6 0x80: From local node to node 7 |
| CPU_READ_COMMAND_REQUEST_NODE_4_7 | Number of requests that a latency measurement is made for Event 0x1E2 | all |
0x01: Read block
0x02: Read block shared 0x04: Read block modified 0x08: Change-to-Dirty 0x10: From local node to node 4 0x20: From local node to node 5 0x40: From local node to node 6 0x80: From local node to node 7 |
| CPU_COMMAND_LATENCY_TARGET | Determine latency between the local node and a remote node. | all |
0x01: Read sized
0x02: Write sized 0x04: Victim block 0x08: Node group select: 0=Nodes 0-3, 1=Nodes 4-7 0x10: From local node to node 0/4 0x20: From local node to node 1/5 0x40: From local node to node 2/6 0x80: From local node to node 3/7 |
| CPU_REQUEST_TARGET | Number of requests that a latency measurement is made for Event 0x1E6 | all |
0x01: Read sized
0x02: Write sized 0x04: Victim block 0x08: Node group select: 0=Nodes 0-3, 1=Nodes 4-7 0x10: From local node to node 0/4 0x20: From local node to node 1/5 0x40: From local node to node 2/6 0x80: From local node to node 3/7 |
| HYPERTRANSPORT_LINK0_TRANSMIT_BANDWIDTH | HyperTransport(tm) link 0 transmit bandwidth | all |
0x01: Command DWORD sent
0x02: Data DWORD sent 0x04: Buffer release DWORD sent 0x08: Nop DW sent (idle) 0x10: Address DWORD sent 0x20: Per packet CRC sent 0x80: SubLink Mask |
| HYPERTRANSPORT_LINK1_TRANSMIT_BANDWIDTH | HyperTransport(tm) link 1 transmit bandwidth | all |
0x01: Command DWORD sent
0x02: Data DWORD sent 0x04: Buffer release DWORD sent 0x08: Nop DW sent (idle) 0x10: Address DWORD sent 0x20: Per packet CRC sent 0x80: SubLink Mask |
| HYPERTRANSPORT_LINK2_TRANSMIT_BANDWIDTH | HyperTransport(tm) link 2 transmit bandwidth | all |
0x01: Command DWORD sent
0x02: Data DWORD sent 0x04: Buffer release DWORD sent 0x08: Nop DW sent (idle) 0x10: Address DWORD sent 0x20: Per packet CRC sent 0x80: SubLink Mask |
| HYPERTRANSPORT_LINK3_TRANSMIT_BANDWIDTH | HyperTransport(tm) link 3 transmit bandwidth | all |
0x01: Command DWORD sent
0x02: Data DWORD sent 0x04: Buffer release DWORD sent 0x08: Nop DW sent (idle) 0x10: Address DWORD sent 0x20: Per packet CRC sent 0x80: SubLink Mask |
| READ_REQUEST_L3_CACHE | Number of read requests from each core to L3 cache | all |
0x01: Read block Exclusive (Data cache read)
0x02: Read block Shared (Instruciton cache read) 0x04: Read block Modify 0x10: Reserved (Must be selected) 0x20: Reserved (Must be selected) 0x40: Reserved (Must be selected) 0x80: Reserved (Must be selected) |
| L3_CACHE_MISSES | Number of L3 cache misses from each core | all |
0x01: Read block Exclusive (Data cache read)
0x02: Read block Shared (Instruciton cache read) 0x04: Read block Modify 0x10: Reserved (Must be selected) 0x20: Reserved (Must be selected) 0x40: Reserved (Must be selected) 0x80: Reserved (Must be selected) |
| L3_FILLS_CAUSED_BY_L2_EVICTIONS | Number of L3 fills caused by L2 evictions per core | all |
0x01: Shared
0x02: Exclusive 0x04: Owned 0x08: Modified 0x10: Reserved (Must be selected) 0x20: Reserved (Must be selected) 0x40: Reserved (Must be selected) 0x80: Reserved (Must be selected) |
| L3_EVICTIONS | Number of L3 cache line evictions by cache state | all |
0x01: Shared
0x02: Exclusive 0x04: Owned 0x08: Modified |
| NON_CANCELLED_L3_READ_REQUESTS | Non-cancelled L3 Read Requests (Rev D) | all |
0x01: RbBlk
0x02: RbBlkS 0x04: RbBlkM 0x10: Reserved (Must be selected) 0x20: Reserved (Must be selected) 0x40: Reserved (Must be selected) 0x80: Reserved (Must be selected) |
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