This is a list AMD Atlhon and Duron CPU's performance counter event types. Please see the AMD Optimization Manual for more details. Note that any counter can be used for any event.
| Name | Description | Counters usable | Unit mask options |
| CPU_CLK_UNHALTED | Cycles outside of halt state | all | |
| RETIRED_INSNS | Retired instructions (includes exceptions, interrupts, resyncs) | all | |
| RETIRED_OPS | Retired Ops | all | |
| ICACHE_FETCHES | Instruction cache fetches | all | |
| ICACHE_MISSES | Instruction cache misses | all | |
| DATA_CACHE_ACCESSES | Data cache accesses | all | |
| DATA_CACHE_MISSES | Data cache misses | all | |
| DATA_CACHE_REFILLS_FROM_L2 | Data cache refills from L2 | all |
0x10: (M)odified cache state
0x08: (O)wner cache state 0x04: (E)xclusive cache state 0x02: (S)hared cache state 0x01: (I)nvalid cache state 0x1f: All cache states |
| DATA_CACHE_REFILLS_FROM_SYSTEM | Data cache refills from system | all |
0x10: (M)odified cache state
0x08: (O)wner cache state 0x04: (E)xclusive cache state 0x02: (S)hared cache state 0x01: (I)nvalid cache state 0x1f: All cache states |
| DATA_CACHE_WRITEBACKS | Data cache write backs | all |
0x10: (M)odified cache state
0x08: (O)wner cache state 0x04: (E)xclusive cache state 0x02: (S)hared cache state 0x01: (I)nvalid cache state 0x1f: All cache states |
| RETIRED_BRANCHES | Retired branches (conditional, unconditional, exceptions, interrupts) | all | |
| RETIRED_BRANCHES_MISPREDICTED | Retired branches mispredicted | all | |
| RETIRED_TAKEN_BRANCHES | Retired taken branches | all | |
| RETIRED_TAKEN_BRANCHES_MISPREDICTED | Retired taken branches mispredicted | all | |
| L1_DTLB_MISSES_L2_DTLD_HITS | L1 DTLB misses and L2 DTLB hits | all | |
| L1_AND_L2_DTLB_MISSES | L1 and L2 DTLB misses | all | |
| MISALIGNED_DATA_REFS | Misaligned data references | all | |
| L1_ITLB_MISSES_L2_ITLB_HITS | L1 ITLB misses (and L2 ITLB hits) | all | |
| L1_AND_L2_ITLB_MISSES | L1 and L2 ITLB misses | all | |
| RETIRED_FAR_CONTROL_TRANSFERS | Retired far control transfers | all | |
| RETIRED_RESYNC_BRANCHES | Retired resync branches (only non-control transfer branches counted) | all | |
| INTERRUPTS_MASKED | Interrupts masked cycles (IF=0) | all | |
| INTERRUPTS_MASKED_PENDING | Interrupts masked while pending cycles (INTR while IF=0) | all | |
| HARDWARE_INTERRUPTS | Number of taken hardware interrupts | all |
Optimizations always bust things, because all optimizations are, in the long haul, a form of cheating, and cheaters eventually get caught.- Larry Wall